6 #if !defined(TARGET_SPARC64)
7 #define TARGET_LONG_BITS 32
8 #define TARGET_FPREGS 32
9 #define TARGET_PAGE_BITS 12 /* 4k */
11 #define TARGET_LONG_BITS 64
12 #define TARGET_FPREGS 64
13 #define TARGET_PAGE_BITS 13 /* 8k */
16 #define TARGET_PHYS_ADDR_BITS 64
20 #include "softfloat.h"
22 #define TARGET_HAS_ICE 1
24 #if !defined(TARGET_SPARC64)
25 #define ELF_MACHINE EM_SPARC
27 #define ELF_MACHINE EM_SPARCV9
30 /*#define EXCP_INTERRUPT 0x100*/
32 /* trap definitions */
33 #ifndef TARGET_SPARC64
34 #define TT_TFAULT 0x01
35 #define TT_ILL_INSN 0x02
36 #define TT_PRIV_INSN 0x03
37 #define TT_NFPU_INSN 0x04
38 #define TT_WIN_OVF 0x05
39 #define TT_WIN_UNF 0x06
40 #define TT_UNALIGNED 0x07
41 #define TT_FP_EXCP 0x08
42 #define TT_DFAULT 0x09
44 #define TT_EXTINT 0x10
45 #define TT_CODE_ACCESS 0x21
46 #define TT_UNIMP_FLUSH 0x25
47 #define TT_DATA_ACCESS 0x29
48 #define TT_DIV_ZERO 0x2a
49 #define TT_NCP_INSN 0x24
52 #define TT_TFAULT 0x08
53 #define TT_CODE_ACCESS 0x0a
54 #define TT_ILL_INSN 0x10
55 #define TT_UNIMP_FLUSH TT_ILL_INSN
56 #define TT_PRIV_INSN 0x11
57 #define TT_NFPU_INSN 0x20
58 #define TT_FP_EXCP 0x21
60 #define TT_CLRWIN 0x24
61 #define TT_DIV_ZERO 0x28
62 #define TT_DFAULT 0x30
63 #define TT_DATA_ACCESS 0x32
64 #define TT_UNALIGNED 0x34
65 #define TT_PRIV_ACT 0x37
66 #define TT_EXTINT 0x40
73 #define TT_WOTHER 0x10
77 #define PSR_NEG_SHIFT 23
78 #define PSR_NEG (1 << PSR_NEG_SHIFT)
79 #define PSR_ZERO_SHIFT 22
80 #define PSR_ZERO (1 << PSR_ZERO_SHIFT)
81 #define PSR_OVF_SHIFT 21
82 #define PSR_OVF (1 << PSR_OVF_SHIFT)
83 #define PSR_CARRY_SHIFT 20
84 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
85 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
86 #define PSR_EF (1<<12)
93 /* Trap base register */
94 #define TBR_BASE_MASK 0xfffff000
96 #if defined(TARGET_SPARC64)
100 #define PS_RED (1<<5)
101 #define PS_PEF (1<<4)
103 #define PS_PRIV (1<<2)
107 #define FPRS_FEF (1<<2)
109 #define HS_PRIV (1<<2)
113 #define FSR_RD1 (1<<31)
114 #define FSR_RD0 (1<<30)
115 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
116 #define FSR_RD_NEAREST 0
117 #define FSR_RD_ZERO FSR_RD0
118 #define FSR_RD_POS FSR_RD1
119 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
121 #define FSR_NVM (1<<27)
122 #define FSR_OFM (1<<26)
123 #define FSR_UFM (1<<25)
124 #define FSR_DZM (1<<24)
125 #define FSR_NXM (1<<23)
126 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
128 #define FSR_NVA (1<<9)
129 #define FSR_OFA (1<<8)
130 #define FSR_UFA (1<<7)
131 #define FSR_DZA (1<<6)
132 #define FSR_NXA (1<<5)
133 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
135 #define FSR_NVC (1<<4)
136 #define FSR_OFC (1<<3)
137 #define FSR_UFC (1<<2)
138 #define FSR_DZC (1<<1)
139 #define FSR_NXC (1<<0)
140 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
142 #define FSR_FTT2 (1<<16)
143 #define FSR_FTT1 (1<<15)
144 #define FSR_FTT0 (1<<14)
145 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
146 #define FSR_FTT_IEEE_EXCP (1 << 14)
147 #define FSR_FTT_UNIMPFPOP (3 << 14)
148 #define FSR_FTT_SEQ_ERROR (4 << 14)
149 #define FSR_FTT_INVAL_FPR (6 << 14)
151 #define FSR_FCC1_SHIFT 11
152 #define FSR_FCC1 (1 << FSR_FCC1_SHIFT)
153 #define FSR_FCC0_SHIFT 10
154 #define FSR_FCC0 (1 << FSR_FCC0_SHIFT)
158 #define MMU_NF (1<<1)
160 #define PTE_ENTRYTYPE_MASK 3
161 #define PTE_ACCESS_MASK 0x1c
162 #define PTE_ACCESS_SHIFT 2
163 #define PTE_PPN_SHIFT 7
164 #define PTE_ADDR_MASK 0xffffff00
166 #define PG_ACCESSED_BIT 5
167 #define PG_MODIFIED_BIT 6
168 #define PG_CACHE_BIT 7
170 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
171 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
172 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
174 /* 3 <= NWINDOWS <= 32. */
175 #define MIN_NWINDOWS 3
176 #define MAX_NWINDOWS 32
178 #if !defined(TARGET_SPARC64)
179 #define NB_MMU_MODES 2
181 #define NB_MMU_MODES 3
182 typedef struct trap_state {
190 typedef struct sparc_def_t {
192 target_ulong iu_version;
193 uint32_t fpu_version;
194 uint32_t mmu_version;
196 uint32_t mmu_ctpr_mask;
197 uint32_t mmu_cxr_mask;
198 uint32_t mmu_sfsr_mask;
199 uint32_t mmu_trcr_mask;
205 #define CPU_FEATURE_FLOAT (1 << 0)
206 #define CPU_FEATURE_FLOAT128 (1 << 1)
207 #define CPU_FEATURE_SWAP (1 << 2)
208 #define CPU_FEATURE_MUL (1 << 3)
209 #define CPU_FEATURE_DIV (1 << 4)
210 #define CPU_FEATURE_FLUSH (1 << 5)
211 #define CPU_FEATURE_FSQRT (1 << 6)
212 #define CPU_FEATURE_FMUL (1 << 7)
213 #define CPU_FEATURE_VIS1 (1 << 8)
214 #define CPU_FEATURE_VIS2 (1 << 9)
215 #define CPU_FEATURE_FSMULD (1 << 10)
216 #define CPU_FEATURE_HYPV (1 << 11)
217 #define CPU_FEATURE_CMT (1 << 12)
218 #define CPU_FEATURE_GL (1 << 13)
219 #ifndef TARGET_SPARC64
220 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
221 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
222 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
223 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
225 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
226 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
227 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
228 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
229 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
231 mmu_us_12, // Ultrasparc < III (64 entry TLB)
232 mmu_us_3, // Ultrasparc III (512 entry TLB)
233 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
238 typedef struct CPUSPARCState {
239 target_ulong gregs[8]; /* general registers */
240 target_ulong *regwptr; /* pointer to current register window */
241 target_ulong pc; /* program counter */
242 target_ulong npc; /* next program counter */
243 target_ulong y; /* multiply/divide register */
245 /* emulator internal flags handling */
246 target_ulong cc_src, cc_src2;
249 target_ulong t0, t1; /* temporaries live across basic blocks */
250 target_ulong cond; /* conditional branch result (XXX: save it in a
251 temporary register when possible) */
253 uint32_t psr; /* processor state register */
254 target_ulong fsr; /* FPU state register */
255 float32 fpr[TARGET_FPREGS]; /* floating point registers */
256 uint32_t cwp; /* index of current register window (extracted
258 uint32_t wim; /* window invalid mask */
259 target_ulong tbr; /* trap base register */
260 int psrs; /* supervisor mode (extracted from PSR) */
261 int psrps; /* previous supervisor mode */
262 int psret; /* enable traps */
263 uint32_t psrpil; /* interrupt blocking level */
264 uint32_t pil_in; /* incoming interrupt level bitmap */
265 int psref; /* enable fpu */
266 target_ulong version;
269 /* NOTE: we allow 8 more registers to handle wrapping */
270 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
275 #if defined(TARGET_SPARC64)
279 uint64_t immuregs[16];
280 uint64_t dmmuregs[16];
281 uint64_t itlb_tag[64];
282 uint64_t itlb_tte[64];
283 uint64_t dtlb_tag[64];
284 uint64_t dtlb_tte[64];
285 uint32_t mmu_version;
287 uint32_t mmuregs[32];
288 uint64_t mxccdata[4];
289 uint64_t mxccregs[8];
292 /* temporary float registers */
296 float_status fp_status;
297 #if defined(TARGET_SPARC64)
299 #define MAXTL_MASK (MAXTL_MAX - 1)
301 trap_state ts[MAXTL_MAX];
302 uint32_t xcc; /* Extended integer condition codes */
307 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
308 uint64_t agregs[8]; /* alternate general registers */
309 uint64_t bgregs[8]; /* backup for normal global registers */
310 uint64_t igregs[8]; /* interrupt general registers */
311 uint64_t mgregs[8]; /* mmu general registers */
313 uint64_t tick_cmpr, stick_cmpr;
316 uint32_t gl; // UA2005
317 /* UA 2005 hyperprivileged registers */
318 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
319 void *hstick; // UA 2005
324 #if defined(TARGET_SPARC64)
325 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
326 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
327 env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
329 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
330 #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
331 env->fsr = _tmp & 0x3fcfc1c3ffULL; \
334 #define GET_FSR32(env) (env->fsr)
335 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
336 env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \
340 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
341 void gen_intermediate_code_init(CPUSPARCState *env);
342 int cpu_sparc_exec(CPUSPARCState *s);
343 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
345 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
347 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
348 (env->psref? PSR_EF : 0) | \
349 (env->psrpil << 8) | \
350 (env->psrs? PSR_S : 0) | \
351 (env->psrps? PSR_PS : 0) | \
352 (env->psret? PSR_ET : 0) | env->cwp)
354 #ifndef NO_CPU_IO_DEFS
355 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
357 static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
359 if (unlikely(cwp >= env1->nwindows))
360 cwp -= env1->nwindows;
364 static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
366 if (unlikely(cwp < 0))
367 cwp += env1->nwindows;
372 #define PUT_PSR(env, val) do { int _tmp = val; \
373 env->psr = _tmp & PSR_ICC; \
374 env->psref = (_tmp & PSR_EF)? 1 : 0; \
375 env->psrpil = (_tmp & PSR_PIL) >> 8; \
376 env->psrs = (_tmp & PSR_S)? 1 : 0; \
377 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
378 env->psret = (_tmp & PSR_ET)? 1 : 0; \
379 cpu_set_cwp(env, _tmp & PSR_CWP); \
382 #ifdef TARGET_SPARC64
383 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
384 #define PUT_CCR(env, val) do { int _tmp = val; \
385 env->xcc = (_tmp >> 4) << 20; \
386 env->psr = (_tmp & 0xf) << 20; \
388 #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
390 #ifndef NO_CPU_IO_DEFS
391 static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
393 if (unlikely(cwp >= env1->nwindows || cwp < 0))
395 cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
400 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
401 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
403 void cpu_check_irqs(CPUSPARCState *env);
405 #define CPUState CPUSPARCState
406 #define cpu_init cpu_sparc_init
407 #define cpu_exec cpu_sparc_exec
408 #define cpu_gen_code cpu_sparc_gen_code
409 #define cpu_signal_handler cpu_sparc_signal_handler
410 #define cpu_list sparc_cpu_list
412 #define CPU_SAVE_VERSION 5
414 /* MMU modes definitions */
415 #define MMU_MODE0_SUFFIX _user
416 #define MMU_MODE1_SUFFIX _kernel
417 #ifdef TARGET_SPARC64
418 #define MMU_MODE2_SUFFIX _hypv
420 #define MMU_USER_IDX 0
421 #define MMU_KERNEL_IDX 1
422 #define MMU_HYPV_IDX 2
424 static inline int cpu_mmu_index(CPUState *env1)
426 #if defined(CONFIG_USER_ONLY)
428 #elif !defined(TARGET_SPARC64)
433 else if ((env1->hpstate & HS_PRIV) == 0)
434 return MMU_KERNEL_IDX;
440 static inline int cpu_fpu_enabled(CPUState *env1)
442 #if defined(CONFIG_USER_ONLY)
444 #elif !defined(TARGET_SPARC64)
447 return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
451 #if defined(CONFIG_USER_ONLY)
452 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
455 env->regwptr[22] = newsp;
457 /* FIXME: Do we also need to clear CF? */
459 printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
463 #define CPU_PC_FROM_TB(env, tb) do { \
465 env->npc = tb->cs_base; \