3 #include "qemu-timer.h"
7 void register_machines(void)
10 qemu_register_machine(&sun4u_machine);
11 qemu_register_machine(&sun4v_machine);
13 qemu_register_machine(&ss5_machine);
14 qemu_register_machine(&ss10_machine);
15 qemu_register_machine(&ss600mp_machine);
16 qemu_register_machine(&ss20_machine);
17 qemu_register_machine(&ss2_machine);
18 qemu_register_machine(&voyager_machine);
19 qemu_register_machine(&ss_lx_machine);
20 qemu_register_machine(&ss4_machine);
21 qemu_register_machine(&scls_machine);
22 qemu_register_machine(&sbook_machine);
23 qemu_register_machine(&ss1000_machine);
24 qemu_register_machine(&ss2000_machine);
28 void cpu_save(QEMUFile *f, void *opaque)
30 CPUState *env = opaque;
34 // if env->cwp == env->nwindows - 1, this will set the ins of the last
35 // window as the outs of the first window
36 cpu_set_cwp(env, env->cwp);
38 for(i = 0; i < 8; i++)
39 qemu_put_betls(f, &env->gregs[i]);
40 qemu_put_be32s(f, &env->nwindows);
41 for(i = 0; i < env->nwindows * 16; i++)
42 qemu_put_betls(f, &env->regbase[i]);
45 for(i = 0; i < TARGET_FPREGS; i++) {
51 qemu_put_be32(f, u.i);
54 qemu_put_betls(f, &env->pc);
55 qemu_put_betls(f, &env->npc);
56 qemu_put_betls(f, &env->y);
58 qemu_put_be32(f, tmp);
59 qemu_put_betls(f, &env->fsr);
60 qemu_put_betls(f, &env->tbr);
61 tmp = env->interrupt_index;
62 qemu_put_be32(f, tmp);
63 qemu_put_be32s(f, &env->pil_in);
64 #ifndef TARGET_SPARC64
65 qemu_put_be32s(f, &env->wim);
67 for (i = 0; i < 32; i++)
68 qemu_put_be32s(f, &env->mmuregs[i]);
70 qemu_put_be64s(f, &env->lsu);
71 for (i = 0; i < 16; i++) {
72 qemu_put_be64s(f, &env->immuregs[i]);
73 qemu_put_be64s(f, &env->dmmuregs[i]);
75 for (i = 0; i < 64; i++) {
76 qemu_put_be64s(f, &env->itlb_tag[i]);
77 qemu_put_be64s(f, &env->itlb_tte[i]);
78 qemu_put_be64s(f, &env->dtlb_tag[i]);
79 qemu_put_be64s(f, &env->dtlb_tte[i]);
81 qemu_put_be32s(f, &env->mmu_version);
82 for (i = 0; i < MAXTL_MAX; i++) {
83 qemu_put_be64s(f, &env->ts[i].tpc);
84 qemu_put_be64s(f, &env->ts[i].tnpc);
85 qemu_put_be64s(f, &env->ts[i].tstate);
86 qemu_put_be32s(f, &env->ts[i].tt);
88 qemu_put_be32s(f, &env->xcc);
89 qemu_put_be32s(f, &env->asi);
90 qemu_put_be32s(f, &env->pstate);
91 qemu_put_be32s(f, &env->tl);
92 qemu_put_be32s(f, &env->cansave);
93 qemu_put_be32s(f, &env->canrestore);
94 qemu_put_be32s(f, &env->otherwin);
95 qemu_put_be32s(f, &env->wstate);
96 qemu_put_be32s(f, &env->cleanwin);
97 for (i = 0; i < 8; i++)
98 qemu_put_be64s(f, &env->agregs[i]);
99 for (i = 0; i < 8; i++)
100 qemu_put_be64s(f, &env->bgregs[i]);
101 for (i = 0; i < 8; i++)
102 qemu_put_be64s(f, &env->igregs[i]);
103 for (i = 0; i < 8; i++)
104 qemu_put_be64s(f, &env->mgregs[i]);
105 qemu_put_be64s(f, &env->fprs);
106 qemu_put_be64s(f, &env->tick_cmpr);
107 qemu_put_be64s(f, &env->stick_cmpr);
108 qemu_put_ptimer(f, env->tick);
109 qemu_put_ptimer(f, env->stick);
110 qemu_put_be64s(f, &env->gsr);
111 qemu_put_be32s(f, &env->gl);
112 qemu_put_be64s(f, &env->hpstate);
113 for (i = 0; i < MAXTL_MAX; i++)
114 qemu_put_be64s(f, &env->htstate[i]);
115 qemu_put_be64s(f, &env->hintp);
116 qemu_put_be64s(f, &env->htba);
117 qemu_put_be64s(f, &env->hver);
118 qemu_put_be64s(f, &env->hstick_cmpr);
119 qemu_put_be64s(f, &env->ssr);
120 qemu_put_ptimer(f, env->hstick);
124 int cpu_load(QEMUFile *f, void *opaque, int version_id)
126 CPUState *env = opaque;
132 for(i = 0; i < 8; i++)
133 qemu_get_betls(f, &env->gregs[i]);
134 qemu_get_be32s(f, &env->nwindows);
135 for(i = 0; i < env->nwindows * 16; i++)
136 qemu_get_betls(f, &env->regbase[i]);
139 for(i = 0; i < TARGET_FPREGS; i++) {
144 u.i = qemu_get_be32(f);
148 qemu_get_betls(f, &env->pc);
149 qemu_get_betls(f, &env->npc);
150 qemu_get_betls(f, &env->y);
151 tmp = qemu_get_be32(f);
152 env->cwp = 0; /* needed to ensure that the wrapping registers are
155 qemu_get_betls(f, &env->fsr);
156 qemu_get_betls(f, &env->tbr);
157 tmp = qemu_get_be32(f);
158 env->interrupt_index = tmp;
159 qemu_get_be32s(f, &env->pil_in);
160 #ifndef TARGET_SPARC64
161 qemu_get_be32s(f, &env->wim);
163 for (i = 0; i < 32; i++)
164 qemu_get_be32s(f, &env->mmuregs[i]);
166 qemu_get_be64s(f, &env->lsu);
167 for (i = 0; i < 16; i++) {
168 qemu_get_be64s(f, &env->immuregs[i]);
169 qemu_get_be64s(f, &env->dmmuregs[i]);
171 for (i = 0; i < 64; i++) {
172 qemu_get_be64s(f, &env->itlb_tag[i]);
173 qemu_get_be64s(f, &env->itlb_tte[i]);
174 qemu_get_be64s(f, &env->dtlb_tag[i]);
175 qemu_get_be64s(f, &env->dtlb_tte[i]);
177 qemu_get_be32s(f, &env->mmu_version);
178 for (i = 0; i < MAXTL_MAX; i++) {
179 qemu_get_be64s(f, &env->ts[i].tpc);
180 qemu_get_be64s(f, &env->ts[i].tnpc);
181 qemu_get_be64s(f, &env->ts[i].tstate);
182 qemu_get_be32s(f, &env->ts[i].tt);
184 qemu_get_be32s(f, &env->xcc);
185 qemu_get_be32s(f, &env->asi);
186 qemu_get_be32s(f, &env->pstate);
187 qemu_get_be32s(f, &env->tl);
188 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
189 qemu_get_be32s(f, &env->cansave);
190 qemu_get_be32s(f, &env->canrestore);
191 qemu_get_be32s(f, &env->otherwin);
192 qemu_get_be32s(f, &env->wstate);
193 qemu_get_be32s(f, &env->cleanwin);
194 for (i = 0; i < 8; i++)
195 qemu_get_be64s(f, &env->agregs[i]);
196 for (i = 0; i < 8; i++)
197 qemu_get_be64s(f, &env->bgregs[i]);
198 for (i = 0; i < 8; i++)
199 qemu_get_be64s(f, &env->igregs[i]);
200 for (i = 0; i < 8; i++)
201 qemu_get_be64s(f, &env->mgregs[i]);
202 qemu_get_be64s(f, &env->fprs);
203 qemu_get_be64s(f, &env->tick_cmpr);
204 qemu_get_be64s(f, &env->stick_cmpr);
205 qemu_get_ptimer(f, env->tick);
206 qemu_get_ptimer(f, env->stick);
207 qemu_get_be64s(f, &env->gsr);
208 qemu_get_be32s(f, &env->gl);
209 qemu_get_be64s(f, &env->hpstate);
210 for (i = 0; i < MAXTL_MAX; i++)
211 qemu_get_be64s(f, &env->htstate[i]);
212 qemu_get_be64s(f, &env->hintp);
213 qemu_get_be64s(f, &env->htba);
214 qemu_get_be64s(f, &env->hver);
215 qemu_get_be64s(f, &env->hstick_cmpr);
216 qemu_get_be64s(f, &env->ssr);
217 qemu_get_ptimer(f, env->hstick);