2 #include "host-utils.h"
4 #if !defined(CONFIG_USER_ONLY)
5 #include "softmmu_exec.h"
6 #endif /* !defined(CONFIG_USER_ONLY) */
10 //#define DEBUG_UNALIGNED
11 //#define DEBUG_UNASSIGNED
16 #define DPRINTF_MMU(fmt, args...) \
17 do { printf("MMU: " fmt , ##args); } while (0)
19 #define DPRINTF_MMU(fmt, args...) do {} while (0)
23 #define DPRINTF_MXCC(fmt, args...) \
24 do { printf("MXCC: " fmt , ##args); } while (0)
26 #define DPRINTF_MXCC(fmt, args...) do {} while (0)
30 #define DPRINTF_ASI(fmt, args...) \
31 do { printf("ASI: " fmt , ##args); } while (0)
33 #define DPRINTF_ASI(fmt, args...) do {} while (0)
38 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
40 #define AM_CHECK(env1) (1)
44 static inline void address_mask(CPUState *env1, target_ulong *addr)
48 *addr &= 0xffffffffULL;
52 void raise_exception(int tt)
54 env->exception_index = tt;
58 static inline void set_cwp(int new_cwp)
60 cpu_set_cwp(env, new_cwp);
63 void helper_check_align(target_ulong addr, uint32_t align)
66 #ifdef DEBUG_UNALIGNED
67 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
70 raise_exception(TT_UNALIGNED);
74 #define F_HELPER(name, p) void helper_f##name##p(void)
76 #define F_BINOP(name) \
77 float32 helper_f ## name ## s (float32 src1, float32 src2) \
79 return float32_ ## name (src1, src2, &env->fp_status); \
83 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
87 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
96 void helper_fsmuld(float32 src1, float32 src2)
98 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
99 float32_to_float64(src2, &env->fp_status),
103 void helper_fdmulq(void)
105 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
106 float64_to_float128(DT1, &env->fp_status),
110 float32 helper_fnegs(float32 src)
112 return float32_chs(src);
115 #ifdef TARGET_SPARC64
118 DT0 = float64_chs(DT1);
123 QT0 = float128_chs(QT1);
127 /* Integer to float conversion. */
128 float32 helper_fitos(int32_t src)
130 return int32_to_float32(src, &env->fp_status);
133 void helper_fitod(int32_t src)
135 DT0 = int32_to_float64(src, &env->fp_status);
138 void helper_fitoq(int32_t src)
140 QT0 = int32_to_float128(src, &env->fp_status);
143 #ifdef TARGET_SPARC64
144 float32 helper_fxtos(void)
146 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
151 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
156 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
161 /* floating point conversion */
162 float32 helper_fdtos(void)
164 return float64_to_float32(DT1, &env->fp_status);
167 void helper_fstod(float32 src)
169 DT0 = float32_to_float64(src, &env->fp_status);
172 float32 helper_fqtos(void)
174 return float128_to_float32(QT1, &env->fp_status);
177 void helper_fstoq(float32 src)
179 QT0 = float32_to_float128(src, &env->fp_status);
182 void helper_fqtod(void)
184 DT0 = float128_to_float64(QT1, &env->fp_status);
187 void helper_fdtoq(void)
189 QT0 = float64_to_float128(DT1, &env->fp_status);
192 /* Float to integer conversion. */
193 int32_t helper_fstoi(float32 src)
195 return float32_to_int32_round_to_zero(src, &env->fp_status);
198 int32_t helper_fdtoi(void)
200 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
203 int32_t helper_fqtoi(void)
205 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
208 #ifdef TARGET_SPARC64
209 void helper_fstox(float32 src)
211 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
214 void helper_fdtox(void)
216 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
219 void helper_fqtox(void)
221 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
224 void helper_faligndata(void)
228 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
229 /* on many architectures a shift of 64 does nothing */
230 if ((env->gsr & 7) != 0) {
231 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
233 *((uint64_t *)&DT0) = tmp;
236 #ifdef WORDS_BIGENDIAN
237 #define VIS_B64(n) b[7 - (n)]
238 #define VIS_W64(n) w[3 - (n)]
239 #define VIS_SW64(n) sw[3 - (n)]
240 #define VIS_L64(n) l[1 - (n)]
241 #define VIS_B32(n) b[3 - (n)]
242 #define VIS_W32(n) w[1 - (n)]
244 #define VIS_B64(n) b[n]
245 #define VIS_W64(n) w[n]
246 #define VIS_SW64(n) sw[n]
247 #define VIS_L64(n) l[n]
248 #define VIS_B32(n) b[n]
249 #define VIS_W32(n) w[n]
267 void helper_fpmerge(void)
274 // Reverse calculation order to handle overlap
275 d.VIS_B64(7) = s.VIS_B64(3);
276 d.VIS_B64(6) = d.VIS_B64(3);
277 d.VIS_B64(5) = s.VIS_B64(2);
278 d.VIS_B64(4) = d.VIS_B64(2);
279 d.VIS_B64(3) = s.VIS_B64(1);
280 d.VIS_B64(2) = d.VIS_B64(1);
281 d.VIS_B64(1) = s.VIS_B64(0);
282 //d.VIS_B64(0) = d.VIS_B64(0);
287 void helper_fmul8x16(void)
296 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
297 if ((tmp & 0xff) > 0x7f) \
299 d.VIS_W64(r) = tmp >> 8;
310 void helper_fmul8x16al(void)
319 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
320 if ((tmp & 0xff) > 0x7f) \
322 d.VIS_W64(r) = tmp >> 8;
333 void helper_fmul8x16au(void)
342 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
343 if ((tmp & 0xff) > 0x7f) \
345 d.VIS_W64(r) = tmp >> 8;
356 void helper_fmul8sux16(void)
365 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
366 if ((tmp & 0xff) > 0x7f) \
368 d.VIS_W64(r) = tmp >> 8;
379 void helper_fmul8ulx16(void)
388 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
389 if ((tmp & 0xff) > 0x7f) \
391 d.VIS_W64(r) = tmp >> 8;
402 void helper_fmuld8sux16(void)
411 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
412 if ((tmp & 0xff) > 0x7f) \
416 // Reverse calculation order to handle overlap
424 void helper_fmuld8ulx16(void)
433 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
434 if ((tmp & 0xff) > 0x7f) \
438 // Reverse calculation order to handle overlap
446 void helper_fexpand(void)
451 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
453 d.VIS_L64(0) = s.VIS_W32(0) << 4;
454 d.VIS_L64(1) = s.VIS_W32(1) << 4;
455 d.VIS_L64(2) = s.VIS_W32(2) << 4;
456 d.VIS_L64(3) = s.VIS_W32(3) << 4;
461 #define VIS_HELPER(name, F) \
462 void name##16(void) \
469 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
470 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
471 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
472 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
477 uint32_t name##16s(uint32_t src1, uint32_t src2) \
484 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
485 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
490 void name##32(void) \
497 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
498 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
503 uint32_t name##32s(uint32_t src1, uint32_t src2) \
515 #define FADD(a, b) ((a) + (b))
516 #define FSUB(a, b) ((a) - (b))
517 VIS_HELPER(helper_fpadd, FADD)
518 VIS_HELPER(helper_fpsub, FSUB)
520 #define VIS_CMPHELPER(name, F) \
521 void name##16(void) \
528 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
529 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
530 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
531 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
536 void name##32(void) \
543 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
544 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
549 #define FCMPGT(a, b) ((a) > (b))
550 #define FCMPEQ(a, b) ((a) == (b))
551 #define FCMPLE(a, b) ((a) <= (b))
552 #define FCMPNE(a, b) ((a) != (b))
554 VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
555 VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
556 VIS_CMPHELPER(helper_fcmple, FCMPLE)
557 VIS_CMPHELPER(helper_fcmpne, FCMPNE)
560 void helper_check_ieee_exceptions(void)
564 status = get_float_exception_flags(&env->fp_status);
566 /* Copy IEEE 754 flags into FSR */
567 if (status & float_flag_invalid)
569 if (status & float_flag_overflow)
571 if (status & float_flag_underflow)
573 if (status & float_flag_divbyzero)
575 if (status & float_flag_inexact)
578 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
579 /* Unmasked exception, generate a trap */
580 env->fsr |= FSR_FTT_IEEE_EXCP;
581 raise_exception(TT_FP_EXCP);
583 /* Accumulate exceptions */
584 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
589 void helper_clear_float_exceptions(void)
591 set_float_exception_flags(0, &env->fp_status);
594 float32 helper_fabss(float32 src)
596 return float32_abs(src);
599 #ifdef TARGET_SPARC64
600 void helper_fabsd(void)
602 DT0 = float64_abs(DT1);
605 void helper_fabsq(void)
607 QT0 = float128_abs(QT1);
611 float32 helper_fsqrts(float32 src)
613 return float32_sqrt(src, &env->fp_status);
616 void helper_fsqrtd(void)
618 DT0 = float64_sqrt(DT1, &env->fp_status);
621 void helper_fsqrtq(void)
623 QT0 = float128_sqrt(QT1, &env->fp_status);
626 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
627 void glue(helper_, name) (void) \
629 target_ulong new_fsr; \
631 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
632 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
633 case float_relation_unordered: \
634 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
635 if ((env->fsr & FSR_NVM) || TRAP) { \
636 env->fsr |= new_fsr; \
637 env->fsr |= FSR_NVC; \
638 env->fsr |= FSR_FTT_IEEE_EXCP; \
639 raise_exception(TT_FP_EXCP); \
641 env->fsr |= FSR_NVA; \
644 case float_relation_less: \
645 new_fsr = FSR_FCC0 << FS; \
647 case float_relation_greater: \
648 new_fsr = FSR_FCC1 << FS; \
654 env->fsr |= new_fsr; \
656 #define GEN_FCMPS(name, size, FS, TRAP) \
657 void glue(helper_, name)(float32 src1, float32 src2) \
659 target_ulong new_fsr; \
661 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
662 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
663 case float_relation_unordered: \
664 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
665 if ((env->fsr & FSR_NVM) || TRAP) { \
666 env->fsr |= new_fsr; \
667 env->fsr |= FSR_NVC; \
668 env->fsr |= FSR_FTT_IEEE_EXCP; \
669 raise_exception(TT_FP_EXCP); \
671 env->fsr |= FSR_NVA; \
674 case float_relation_less: \
675 new_fsr = FSR_FCC0 << FS; \
677 case float_relation_greater: \
678 new_fsr = FSR_FCC1 << FS; \
684 env->fsr |= new_fsr; \
687 GEN_FCMPS(fcmps, float32, 0, 0);
688 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
690 GEN_FCMPS(fcmpes, float32, 0, 1);
691 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
693 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
694 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
696 #ifdef TARGET_SPARC64
697 GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
698 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
699 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
701 GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
702 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
703 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
705 GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
706 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
707 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
709 GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
710 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
711 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
713 GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
714 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
715 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
717 GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
718 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
719 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
723 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
725 static void dump_mxcc(CPUState *env)
727 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
728 env->mxccdata[0], env->mxccdata[1],
729 env->mxccdata[2], env->mxccdata[3]);
730 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
731 " %016llx %016llx %016llx %016llx\n",
732 env->mxccregs[0], env->mxccregs[1],
733 env->mxccregs[2], env->mxccregs[3],
734 env->mxccregs[4], env->mxccregs[5],
735 env->mxccregs[6], env->mxccregs[7]);
739 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
740 && defined(DEBUG_ASI)
741 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
747 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
748 addr, asi, r1 & 0xff);
751 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
752 addr, asi, r1 & 0xffff);
755 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
756 addr, asi, r1 & 0xffffffff);
759 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
766 #ifndef TARGET_SPARC64
767 #ifndef CONFIG_USER_ONLY
768 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
771 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
772 uint32_t last_addr = addr;
775 helper_check_align(addr, size - 1);
777 case 2: /* SuperSparc MXCC registers */
779 case 0x01c00a00: /* MXCC control register */
781 ret = env->mxccregs[3];
783 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
786 case 0x01c00a04: /* MXCC control register */
788 ret = env->mxccregs[3];
790 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
793 case 0x01c00c00: /* Module reset register */
795 ret = env->mxccregs[5];
796 // should we do something here?
798 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
801 case 0x01c00f00: /* MBus port address register */
803 ret = env->mxccregs[7];
805 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
809 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
813 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
814 "addr = %08x -> ret = %08x,"
815 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
820 case 3: /* MMU probe */
824 mmulev = (addr >> 8) & 15;
828 ret = mmu_probe(env, addr, mmulev);
829 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
833 case 4: /* read MMU regs */
835 int reg = (addr >> 8) & 0x1f;
837 ret = env->mmuregs[reg];
838 if (reg == 3) /* Fault status cleared on read */
840 else if (reg == 0x13) /* Fault status read */
841 ret = env->mmuregs[3];
842 else if (reg == 0x14) /* Fault address read */
843 ret = env->mmuregs[4];
844 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
847 case 5: // Turbosparc ITLB Diagnostic
848 case 6: // Turbosparc DTLB Diagnostic
849 case 7: // Turbosparc IOTLB Diagnostic
851 case 9: /* Supervisor code access */
854 ret = ldub_code(addr);
857 ret = lduw_code(addr);
861 ret = ldl_code(addr);
864 ret = ldq_code(addr);
868 case 0xa: /* User data access */
871 ret = ldub_user(addr);
874 ret = lduw_user(addr);
878 ret = ldl_user(addr);
881 ret = ldq_user(addr);
885 case 0xb: /* Supervisor data access */
888 ret = ldub_kernel(addr);
891 ret = lduw_kernel(addr);
895 ret = ldl_kernel(addr);
898 ret = ldq_kernel(addr);
902 case 0xc: /* I-cache tag */
903 case 0xd: /* I-cache data */
904 case 0xe: /* D-cache tag */
905 case 0xf: /* D-cache data */
907 case 0x20: /* MMU passthrough */
910 ret = ldub_phys(addr);
913 ret = lduw_phys(addr);
917 ret = ldl_phys(addr);
920 ret = ldq_phys(addr);
924 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
927 ret = ldub_phys((target_phys_addr_t)addr
928 | ((target_phys_addr_t)(asi & 0xf) << 32));
931 ret = lduw_phys((target_phys_addr_t)addr
932 | ((target_phys_addr_t)(asi & 0xf) << 32));
936 ret = ldl_phys((target_phys_addr_t)addr
937 | ((target_phys_addr_t)(asi & 0xf) << 32));
940 ret = ldq_phys((target_phys_addr_t)addr
941 | ((target_phys_addr_t)(asi & 0xf) << 32));
945 case 0x30: // Turbosparc secondary cache diagnostic
946 case 0x31: // Turbosparc RAM snoop
947 case 0x32: // Turbosparc page table descriptor diagnostic
948 case 0x39: /* data cache diagnostic register */
951 case 8: /* User code access, XXX */
953 do_unassigned_access(addr, 0, 0, asi);
973 dump_asi("read ", last_addr, asi, size, ret);
978 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
980 helper_check_align(addr, size - 1);
982 case 2: /* SuperSparc MXCC registers */
984 case 0x01c00000: /* MXCC stream data register 0 */
986 env->mxccdata[0] = val;
988 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
991 case 0x01c00008: /* MXCC stream data register 1 */
993 env->mxccdata[1] = val;
995 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
998 case 0x01c00010: /* MXCC stream data register 2 */
1000 env->mxccdata[2] = val;
1002 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1005 case 0x01c00018: /* MXCC stream data register 3 */
1007 env->mxccdata[3] = val;
1009 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1012 case 0x01c00100: /* MXCC stream source */
1014 env->mxccregs[0] = val;
1016 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1018 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1020 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1022 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1024 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1027 case 0x01c00200: /* MXCC stream destination */
1029 env->mxccregs[1] = val;
1031 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1033 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1035 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1037 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1039 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1042 case 0x01c00a00: /* MXCC control register */
1044 env->mxccregs[3] = val;
1046 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1049 case 0x01c00a04: /* MXCC control register */
1051 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
1054 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1057 case 0x01c00e00: /* MXCC error register */
1058 // writing a 1 bit clears the error
1060 env->mxccregs[6] &= ~val;
1062 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1065 case 0x01c00f00: /* MBus port address register */
1067 env->mxccregs[7] = val;
1069 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1073 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1077 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi,
1083 case 3: /* MMU flush */
1087 mmulev = (addr >> 8) & 15;
1088 DPRINTF_MMU("mmu flush level %d\n", mmulev);
1090 case 0: // flush page
1091 tlb_flush_page(env, addr & 0xfffff000);
1093 case 1: // flush segment (256k)
1094 case 2: // flush region (16M)
1095 case 3: // flush context (4G)
1096 case 4: // flush entire
1107 case 4: /* write MMU regs */
1109 int reg = (addr >> 8) & 0x1f;
1112 oldreg = env->mmuregs[reg];
1114 case 0: // Control Register
1115 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1117 // Mappings generated during no-fault mode or MMU
1118 // disabled mode are invalid in normal mode
1119 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1120 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
1123 case 1: // Context Table Pointer Register
1124 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
1126 case 2: // Context Register
1127 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
1128 if (oldreg != env->mmuregs[reg]) {
1129 /* we flush when the MMU context changes because
1130 QEMU has no MMU context support */
1134 case 3: // Synchronous Fault Status Register with Clear
1135 case 4: // Synchronous Fault Address Register
1137 case 0x10: // TLB Replacement Control Register
1138 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
1140 case 0x13: // Synchronous Fault Status Register with Read and Clear
1141 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
1143 case 0x14: // Synchronous Fault Address Register
1144 env->mmuregs[4] = val;
1147 env->mmuregs[reg] = val;
1150 if (oldreg != env->mmuregs[reg]) {
1151 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1152 reg, oldreg, env->mmuregs[reg]);
1159 case 5: // Turbosparc ITLB Diagnostic
1160 case 6: // Turbosparc DTLB Diagnostic
1161 case 7: // Turbosparc IOTLB Diagnostic
1163 case 0xa: /* User data access */
1166 stb_user(addr, val);
1169 stw_user(addr, val);
1173 stl_user(addr, val);
1176 stq_user(addr, val);
1180 case 0xb: /* Supervisor data access */
1183 stb_kernel(addr, val);
1186 stw_kernel(addr, val);
1190 stl_kernel(addr, val);
1193 stq_kernel(addr, val);
1197 case 0xc: /* I-cache tag */
1198 case 0xd: /* I-cache data */
1199 case 0xe: /* D-cache tag */
1200 case 0xf: /* D-cache data */
1201 case 0x10: /* I/D-cache flush page */
1202 case 0x11: /* I/D-cache flush segment */
1203 case 0x12: /* I/D-cache flush region */
1204 case 0x13: /* I/D-cache flush context */
1205 case 0x14: /* I/D-cache flush user */
1207 case 0x17: /* Block copy, sta access */
1213 uint32_t src = val & ~3, dst = addr & ~3, temp;
1215 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1216 temp = ldl_kernel(src);
1217 stl_kernel(dst, temp);
1221 case 0x1f: /* Block fill, stda access */
1224 // fill 32 bytes with val
1226 uint32_t dst = addr & 7;
1228 for (i = 0; i < 32; i += 8, dst += 8)
1229 stq_kernel(dst, val);
1232 case 0x20: /* MMU passthrough */
1236 stb_phys(addr, val);
1239 stw_phys(addr, val);
1243 stl_phys(addr, val);
1246 stq_phys(addr, val);
1251 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1255 stb_phys((target_phys_addr_t)addr
1256 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1259 stw_phys((target_phys_addr_t)addr
1260 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1264 stl_phys((target_phys_addr_t)addr
1265 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1268 stq_phys((target_phys_addr_t)addr
1269 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1274 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1275 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1276 // Turbosparc snoop RAM
1277 case 0x32: // store buffer control or Turbosparc page table
1278 // descriptor diagnostic
1279 case 0x36: /* I-cache flash clear */
1280 case 0x37: /* D-cache flash clear */
1281 case 0x38: /* breakpoint diagnostics */
1282 case 0x4c: /* breakpoint action */
1284 case 8: /* User code access, XXX */
1285 case 9: /* Supervisor code access, XXX */
1287 do_unassigned_access(addr, 1, 0, asi);
1291 dump_asi("write", addr, asi, size, val);
1295 #endif /* CONFIG_USER_ONLY */
1296 #else /* TARGET_SPARC64 */
1298 #ifdef CONFIG_USER_ONLY
1299 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1302 #if defined(DEBUG_ASI)
1303 target_ulong last_addr = addr;
1307 raise_exception(TT_PRIV_ACT);
1309 helper_check_align(addr, size - 1);
1310 address_mask(env, &addr);
1313 case 0x82: // Primary no-fault
1314 case 0x8a: // Primary no-fault LE
1315 if (page_check_range(addr, size, PAGE_READ) == -1) {
1317 dump_asi("read ", last_addr, asi, size, ret);
1322 case 0x80: // Primary
1323 case 0x88: // Primary LE
1327 ret = ldub_raw(addr);
1330 ret = lduw_raw(addr);
1333 ret = ldl_raw(addr);
1337 ret = ldq_raw(addr);
1342 case 0x83: // Secondary no-fault
1343 case 0x8b: // Secondary no-fault LE
1344 if (page_check_range(addr, size, PAGE_READ) == -1) {
1346 dump_asi("read ", last_addr, asi, size, ret);
1351 case 0x81: // Secondary
1352 case 0x89: // Secondary LE
1359 /* Convert from little endian */
1361 case 0x88: // Primary LE
1362 case 0x89: // Secondary LE
1363 case 0x8a: // Primary no-fault LE
1364 case 0x8b: // Secondary no-fault LE
1382 /* Convert to signed number */
1389 ret = (int16_t) ret;
1392 ret = (int32_t) ret;
1399 dump_asi("read ", last_addr, asi, size, ret);
1404 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1407 dump_asi("write", addr, asi, size, val);
1410 raise_exception(TT_PRIV_ACT);
1412 helper_check_align(addr, size - 1);
1413 address_mask(env, &addr);
1415 /* Convert to little endian */
1417 case 0x88: // Primary LE
1418 case 0x89: // Secondary LE
1421 addr = bswap16(addr);
1424 addr = bswap32(addr);
1427 addr = bswap64(addr);
1437 case 0x80: // Primary
1438 case 0x88: // Primary LE
1457 case 0x81: // Secondary
1458 case 0x89: // Secondary LE
1462 case 0x82: // Primary no-fault, RO
1463 case 0x83: // Secondary no-fault, RO
1464 case 0x8a: // Primary no-fault LE, RO
1465 case 0x8b: // Secondary no-fault LE, RO
1467 do_unassigned_access(addr, 1, 0, 1);
1472 #else /* CONFIG_USER_ONLY */
1474 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1477 #if defined(DEBUG_ASI)
1478 target_ulong last_addr = addr;
1481 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1482 || ((env->def->features & CPU_FEATURE_HYPV)
1483 && asi >= 0x30 && asi < 0x80
1484 && !(env->hpstate & HS_PRIV)))
1485 raise_exception(TT_PRIV_ACT);
1487 helper_check_align(addr, size - 1);
1489 case 0x82: // Primary no-fault
1490 case 0x8a: // Primary no-fault LE
1491 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1493 dump_asi("read ", last_addr, asi, size, ret);
1498 case 0x10: // As if user primary
1499 case 0x18: // As if user primary LE
1500 case 0x80: // Primary
1501 case 0x88: // Primary LE
1502 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1503 if ((env->def->features & CPU_FEATURE_HYPV)
1504 && env->hpstate & HS_PRIV) {
1507 ret = ldub_hypv(addr);
1510 ret = lduw_hypv(addr);
1513 ret = ldl_hypv(addr);
1517 ret = ldq_hypv(addr);
1523 ret = ldub_kernel(addr);
1526 ret = lduw_kernel(addr);
1529 ret = ldl_kernel(addr);
1533 ret = ldq_kernel(addr);
1540 ret = ldub_user(addr);
1543 ret = lduw_user(addr);
1546 ret = ldl_user(addr);
1550 ret = ldq_user(addr);
1555 case 0x14: // Bypass
1556 case 0x15: // Bypass, non-cacheable
1557 case 0x1c: // Bypass LE
1558 case 0x1d: // Bypass, non-cacheable LE
1562 ret = ldub_phys(addr);
1565 ret = lduw_phys(addr);
1568 ret = ldl_phys(addr);
1572 ret = ldq_phys(addr);
1577 case 0x24: // Nucleus quad LDD 128 bit atomic
1578 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1579 // Only ldda allowed
1580 raise_exception(TT_ILL_INSN);
1582 case 0x83: // Secondary no-fault
1583 case 0x8b: // Secondary no-fault LE
1584 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
1586 dump_asi("read ", last_addr, asi, size, ret);
1591 case 0x04: // Nucleus
1592 case 0x0c: // Nucleus Little Endian (LE)
1593 case 0x11: // As if user secondary
1594 case 0x19: // As if user secondary LE
1595 case 0x4a: // UPA config
1596 case 0x81: // Secondary
1597 case 0x89: // Secondary LE
1603 case 0x50: // I-MMU regs
1605 int reg = (addr >> 3) & 0xf;
1607 ret = env->immuregs[reg];
1610 case 0x51: // I-MMU 8k TSB pointer
1611 case 0x52: // I-MMU 64k TSB pointer
1614 case 0x55: // I-MMU data access
1616 int reg = (addr >> 3) & 0x3f;
1618 ret = env->itlb_tte[reg];
1621 case 0x56: // I-MMU tag read
1623 int reg = (addr >> 3) & 0x3f;
1625 ret = env->itlb_tag[reg];
1628 case 0x58: // D-MMU regs
1630 int reg = (addr >> 3) & 0xf;
1632 ret = env->dmmuregs[reg];
1635 case 0x5d: // D-MMU data access
1637 int reg = (addr >> 3) & 0x3f;
1639 ret = env->dtlb_tte[reg];
1642 case 0x5e: // D-MMU tag read
1644 int reg = (addr >> 3) & 0x3f;
1646 ret = env->dtlb_tag[reg];
1649 case 0x46: // D-cache data
1650 case 0x47: // D-cache tag access
1651 case 0x4b: // E-cache error enable
1652 case 0x4c: // E-cache asynchronous fault status
1653 case 0x4d: // E-cache asynchronous fault address
1654 case 0x4e: // E-cache tag data
1655 case 0x66: // I-cache instruction access
1656 case 0x67: // I-cache tag access
1657 case 0x6e: // I-cache predecode
1658 case 0x6f: // I-cache LRU etc.
1659 case 0x76: // E-cache tag
1660 case 0x7e: // E-cache tag
1662 case 0x59: // D-MMU 8k TSB pointer
1663 case 0x5a: // D-MMU 64k TSB pointer
1664 case 0x5b: // D-MMU data pointer
1665 case 0x48: // Interrupt dispatch, RO
1666 case 0x49: // Interrupt data receive
1667 case 0x7f: // Incoming interrupt vector, RO
1670 case 0x54: // I-MMU data in, WO
1671 case 0x57: // I-MMU demap, WO
1672 case 0x5c: // D-MMU data in, WO
1673 case 0x5f: // D-MMU demap, WO
1674 case 0x77: // Interrupt vector, WO
1676 do_unassigned_access(addr, 0, 0, 1);
1681 /* Convert from little endian */
1683 case 0x0c: // Nucleus Little Endian (LE)
1684 case 0x18: // As if user primary LE
1685 case 0x19: // As if user secondary LE
1686 case 0x1c: // Bypass LE
1687 case 0x1d: // Bypass, non-cacheable LE
1688 case 0x88: // Primary LE
1689 case 0x89: // Secondary LE
1690 case 0x8a: // Primary no-fault LE
1691 case 0x8b: // Secondary no-fault LE
1709 /* Convert to signed number */
1716 ret = (int16_t) ret;
1719 ret = (int32_t) ret;
1726 dump_asi("read ", last_addr, asi, size, ret);
1731 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
1734 dump_asi("write", addr, asi, size, val);
1736 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1737 || ((env->def->features & CPU_FEATURE_HYPV)
1738 && asi >= 0x30 && asi < 0x80
1739 && !(env->hpstate & HS_PRIV)))
1740 raise_exception(TT_PRIV_ACT);
1742 helper_check_align(addr, size - 1);
1743 /* Convert to little endian */
1745 case 0x0c: // Nucleus Little Endian (LE)
1746 case 0x18: // As if user primary LE
1747 case 0x19: // As if user secondary LE
1748 case 0x1c: // Bypass LE
1749 case 0x1d: // Bypass, non-cacheable LE
1750 case 0x88: // Primary LE
1751 case 0x89: // Secondary LE
1754 addr = bswap16(addr);
1757 addr = bswap32(addr);
1760 addr = bswap64(addr);
1770 case 0x10: // As if user primary
1771 case 0x18: // As if user primary LE
1772 case 0x80: // Primary
1773 case 0x88: // Primary LE
1774 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1775 if ((env->def->features & CPU_FEATURE_HYPV)
1776 && env->hpstate & HS_PRIV) {
1779 stb_hypv(addr, val);
1782 stw_hypv(addr, val);
1785 stl_hypv(addr, val);
1789 stq_hypv(addr, val);
1795 stb_kernel(addr, val);
1798 stw_kernel(addr, val);
1801 stl_kernel(addr, val);
1805 stq_kernel(addr, val);
1812 stb_user(addr, val);
1815 stw_user(addr, val);
1818 stl_user(addr, val);
1822 stq_user(addr, val);
1827 case 0x14: // Bypass
1828 case 0x15: // Bypass, non-cacheable
1829 case 0x1c: // Bypass LE
1830 case 0x1d: // Bypass, non-cacheable LE
1834 stb_phys(addr, val);
1837 stw_phys(addr, val);
1840 stl_phys(addr, val);
1844 stq_phys(addr, val);
1849 case 0x24: // Nucleus quad LDD 128 bit atomic
1850 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
1851 // Only ldda allowed
1852 raise_exception(TT_ILL_INSN);
1854 case 0x04: // Nucleus
1855 case 0x0c: // Nucleus Little Endian (LE)
1856 case 0x11: // As if user secondary
1857 case 0x19: // As if user secondary LE
1858 case 0x4a: // UPA config
1859 case 0x81: // Secondary
1860 case 0x89: // Secondary LE
1868 env->lsu = val & (DMMU_E | IMMU_E);
1869 // Mappings generated during D/I MMU disabled mode are
1870 // invalid in normal mode
1871 if (oldreg != env->lsu) {
1872 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1881 case 0x50: // I-MMU regs
1883 int reg = (addr >> 3) & 0xf;
1886 oldreg = env->immuregs[reg];
1891 case 1: // Not in I-MMU
1898 val = 0; // Clear SFSR
1900 case 5: // TSB access
1901 case 6: // Tag access
1905 env->immuregs[reg] = val;
1906 if (oldreg != env->immuregs[reg]) {
1907 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
1908 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1915 case 0x54: // I-MMU data in
1919 // Try finding an invalid entry
1920 for (i = 0; i < 64; i++) {
1921 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1922 env->itlb_tag[i] = env->immuregs[6];
1923 env->itlb_tte[i] = val;
1927 // Try finding an unlocked entry
1928 for (i = 0; i < 64; i++) {
1929 if ((env->itlb_tte[i] & 0x40) == 0) {
1930 env->itlb_tag[i] = env->immuregs[6];
1931 env->itlb_tte[i] = val;
1938 case 0x55: // I-MMU data access
1940 unsigned int i = (addr >> 3) & 0x3f;
1942 env->itlb_tag[i] = env->immuregs[6];
1943 env->itlb_tte[i] = val;
1946 case 0x57: // I-MMU demap
1949 case 0x58: // D-MMU regs
1951 int reg = (addr >> 3) & 0xf;
1954 oldreg = env->dmmuregs[reg];
1960 if ((val & 1) == 0) {
1961 val = 0; // Clear SFSR, Fault address
1962 env->dmmuregs[4] = 0;
1964 env->dmmuregs[reg] = val;
1966 case 1: // Primary context
1967 case 2: // Secondary context
1968 case 5: // TSB access
1969 case 6: // Tag access
1970 case 7: // Virtual Watchpoint
1971 case 8: // Physical Watchpoint
1975 env->dmmuregs[reg] = val;
1976 if (oldreg != env->dmmuregs[reg]) {
1977 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08"
1978 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1985 case 0x5c: // D-MMU data in
1989 // Try finding an invalid entry
1990 for (i = 0; i < 64; i++) {
1991 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1992 env->dtlb_tag[i] = env->dmmuregs[6];
1993 env->dtlb_tte[i] = val;
1997 // Try finding an unlocked entry
1998 for (i = 0; i < 64; i++) {
1999 if ((env->dtlb_tte[i] & 0x40) == 0) {
2000 env->dtlb_tag[i] = env->dmmuregs[6];
2001 env->dtlb_tte[i] = val;
2008 case 0x5d: // D-MMU data access
2010 unsigned int i = (addr >> 3) & 0x3f;
2012 env->dtlb_tag[i] = env->dmmuregs[6];
2013 env->dtlb_tte[i] = val;
2016 case 0x5f: // D-MMU demap
2017 case 0x49: // Interrupt data receive
2020 case 0x46: // D-cache data
2021 case 0x47: // D-cache tag access
2022 case 0x4b: // E-cache error enable
2023 case 0x4c: // E-cache asynchronous fault status
2024 case 0x4d: // E-cache asynchronous fault address
2025 case 0x4e: // E-cache tag data
2026 case 0x66: // I-cache instruction access
2027 case 0x67: // I-cache tag access
2028 case 0x6e: // I-cache predecode
2029 case 0x6f: // I-cache LRU etc.
2030 case 0x76: // E-cache tag
2031 case 0x7e: // E-cache tag
2033 case 0x51: // I-MMU 8k TSB pointer, RO
2034 case 0x52: // I-MMU 64k TSB pointer, RO
2035 case 0x56: // I-MMU tag read, RO
2036 case 0x59: // D-MMU 8k TSB pointer, RO
2037 case 0x5a: // D-MMU 64k TSB pointer, RO
2038 case 0x5b: // D-MMU data pointer, RO
2039 case 0x5e: // D-MMU tag read, RO
2040 case 0x48: // Interrupt dispatch, RO
2041 case 0x7f: // Incoming interrupt vector, RO
2042 case 0x82: // Primary no-fault, RO
2043 case 0x83: // Secondary no-fault, RO
2044 case 0x8a: // Primary no-fault LE, RO
2045 case 0x8b: // Secondary no-fault LE, RO
2047 do_unassigned_access(addr, 1, 0, 1);
2051 #endif /* CONFIG_USER_ONLY */
2053 void helper_ldda_asi(target_ulong addr, int asi, int rd)
2055 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2056 || ((env->def->features & CPU_FEATURE_HYPV)
2057 && asi >= 0x30 && asi < 0x80
2058 && !(env->hpstate & HS_PRIV)))
2059 raise_exception(TT_PRIV_ACT);
2062 case 0x24: // Nucleus quad LDD 128 bit atomic
2063 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2064 helper_check_align(addr, 0xf);
2066 env->gregs[1] = ldq_kernel(addr + 8);
2068 bswap64s(&env->gregs[1]);
2069 } else if (rd < 8) {
2070 env->gregs[rd] = ldq_kernel(addr);
2071 env->gregs[rd + 1] = ldq_kernel(addr + 8);
2073 bswap64s(&env->gregs[rd]);
2074 bswap64s(&env->gregs[rd + 1]);
2077 env->regwptr[rd] = ldq_kernel(addr);
2078 env->regwptr[rd + 1] = ldq_kernel(addr + 8);
2080 bswap64s(&env->regwptr[rd]);
2081 bswap64s(&env->regwptr[rd + 1]);
2086 helper_check_align(addr, 0x3);
2088 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2090 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2091 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2093 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2094 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2100 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2105 helper_check_align(addr, 3);
2107 case 0xf0: // Block load primary
2108 case 0xf1: // Block load secondary
2109 case 0xf8: // Block load primary LE
2110 case 0xf9: // Block load secondary LE
2112 raise_exception(TT_ILL_INSN);
2115 helper_check_align(addr, 0x3f);
2116 for (i = 0; i < 16; i++) {
2117 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2127 val = helper_ld_asi(addr, asi, size, 0);
2131 *((uint32_t *)&env->fpr[rd]) = val;
2134 *((int64_t *)&DT0) = val;
2142 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
2145 target_ulong val = 0;
2147 helper_check_align(addr, 3);
2149 case 0xf0: // Block store primary
2150 case 0xf1: // Block store secondary
2151 case 0xf8: // Block store primary LE
2152 case 0xf9: // Block store secondary LE
2154 raise_exception(TT_ILL_INSN);
2157 helper_check_align(addr, 0x3f);
2158 for (i = 0; i < 16; i++) {
2159 val = *(uint32_t *)&env->fpr[rd++];
2160 helper_st_asi(addr, val, asi & 0x8f, 4);
2172 val = *((uint32_t *)&env->fpr[rd]);
2175 val = *((int64_t *)&DT0);
2181 helper_st_asi(addr, val, asi, size);
2184 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2185 target_ulong val2, uint32_t asi)
2189 val2 &= 0xffffffffUL;
2190 ret = helper_ld_asi(addr, asi, 4, 0);
2191 ret &= 0xffffffffUL;
2193 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
2197 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2198 target_ulong val2, uint32_t asi)
2202 ret = helper_ld_asi(addr, asi, 8, 0);
2204 helper_st_asi(addr, val1, asi, 8);
2207 #endif /* TARGET_SPARC64 */
2209 #ifndef TARGET_SPARC64
2210 void helper_rett(void)
2214 if (env->psret == 1)
2215 raise_exception(TT_ILL_INSN);
2218 cwp = cpu_cwp_inc(env, env->cwp + 1) ;
2219 if (env->wim & (1 << cwp)) {
2220 raise_exception(TT_WIN_UNF);
2223 env->psrs = env->psrps;
2227 target_ulong helper_udiv(target_ulong a, target_ulong b)
2232 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2236 raise_exception(TT_DIV_ZERO);
2240 if (x0 > 0xffffffff) {
2249 target_ulong helper_sdiv(target_ulong a, target_ulong b)
2254 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2258 raise_exception(TT_DIV_ZERO);
2262 if ((int32_t) x0 != x0) {
2264 return x0 < 0? 0x80000000: 0x7fffffff;
2271 void helper_stdf(target_ulong addr, int mem_idx)
2273 helper_check_align(addr, 7);
2274 #if !defined(CONFIG_USER_ONLY)
2277 stfq_user(addr, DT0);
2280 stfq_kernel(addr, DT0);
2282 #ifdef TARGET_SPARC64
2284 stfq_hypv(addr, DT0);
2291 address_mask(env, &addr);
2292 stfq_raw(addr, DT0);
2296 void helper_lddf(target_ulong addr, int mem_idx)
2298 helper_check_align(addr, 7);
2299 #if !defined(CONFIG_USER_ONLY)
2302 DT0 = ldfq_user(addr);
2305 DT0 = ldfq_kernel(addr);
2307 #ifdef TARGET_SPARC64
2309 DT0 = ldfq_hypv(addr);
2316 address_mask(env, &addr);
2317 DT0 = ldfq_raw(addr);
2321 void helper_ldqf(target_ulong addr, int mem_idx)
2323 // XXX add 128 bit load
2326 helper_check_align(addr, 7);
2327 #if !defined(CONFIG_USER_ONLY)
2330 u.ll.upper = ldq_user(addr);
2331 u.ll.lower = ldq_user(addr + 8);
2335 u.ll.upper = ldq_kernel(addr);
2336 u.ll.lower = ldq_kernel(addr + 8);
2339 #ifdef TARGET_SPARC64
2341 u.ll.upper = ldq_hypv(addr);
2342 u.ll.lower = ldq_hypv(addr + 8);
2350 address_mask(env, &addr);
2351 u.ll.upper = ldq_raw(addr);
2352 u.ll.lower = ldq_raw((addr + 8) & 0xffffffffULL);
2357 void helper_stqf(target_ulong addr, int mem_idx)
2359 // XXX add 128 bit store
2362 helper_check_align(addr, 7);
2363 #if !defined(CONFIG_USER_ONLY)
2367 stq_user(addr, u.ll.upper);
2368 stq_user(addr + 8, u.ll.lower);
2372 stq_kernel(addr, u.ll.upper);
2373 stq_kernel(addr + 8, u.ll.lower);
2375 #ifdef TARGET_SPARC64
2378 stq_hypv(addr, u.ll.upper);
2379 stq_hypv(addr + 8, u.ll.lower);
2387 address_mask(env, &addr);
2388 stq_raw(addr, u.ll.upper);
2389 stq_raw((addr + 8) & 0xffffffffULL, u.ll.lower);
2393 static inline void set_fsr(void)
2397 switch (env->fsr & FSR_RD_MASK) {
2398 case FSR_RD_NEAREST:
2399 rnd_mode = float_round_nearest_even;
2403 rnd_mode = float_round_to_zero;
2406 rnd_mode = float_round_up;
2409 rnd_mode = float_round_down;
2412 set_float_rounding_mode(rnd_mode, &env->fp_status);
2415 void helper_ldfsr(uint32_t new_fsr)
2417 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
2421 #ifdef TARGET_SPARC64
2422 void helper_ldxfsr(uint64_t new_fsr)
2424 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
2429 void helper_debug(void)
2431 env->exception_index = EXCP_DEBUG;
2435 #ifndef TARGET_SPARC64
2436 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2438 void helper_save(void)
2442 cwp = cpu_cwp_dec(env, env->cwp - 1);
2443 if (env->wim & (1 << cwp)) {
2444 raise_exception(TT_WIN_OVF);
2449 void helper_restore(void)
2453 cwp = cpu_cwp_inc(env, env->cwp + 1);
2454 if (env->wim & (1 << cwp)) {
2455 raise_exception(TT_WIN_UNF);
2460 void helper_wrpsr(target_ulong new_psr)
2462 if ((new_psr & PSR_CWP) >= env->nwindows)
2463 raise_exception(TT_ILL_INSN);
2465 PUT_PSR(env, new_psr);
2468 target_ulong helper_rdpsr(void)
2470 return GET_PSR(env);
2474 /* XXX: use another pointer for %iN registers to avoid slow wrapping
2476 void helper_save(void)
2480 cwp = cpu_cwp_dec(env, env->cwp - 1);
2481 if (env->cansave == 0) {
2482 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2483 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2484 ((env->wstate & 0x7) << 2)));
2486 if (env->cleanwin - env->canrestore == 0) {
2487 // XXX Clean windows without trap
2488 raise_exception(TT_CLRWIN);
2497 void helper_restore(void)
2501 cwp = cpu_cwp_inc(env, env->cwp + 1);
2502 if (env->canrestore == 0) {
2503 raise_exception(TT_FILL | (env->otherwin != 0 ?
2504 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2505 ((env->wstate & 0x7) << 2)));
2513 void helper_flushw(void)
2515 if (env->cansave != env->nwindows - 2) {
2516 raise_exception(TT_SPILL | (env->otherwin != 0 ?
2517 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
2518 ((env->wstate & 0x7) << 2)));
2522 void helper_saved(void)
2525 if (env->otherwin == 0)
2531 void helper_restored(void)
2534 if (env->cleanwin < env->nwindows - 1)
2536 if (env->otherwin == 0)
2542 target_ulong helper_rdccr(void)
2544 return GET_CCR(env);
2547 void helper_wrccr(target_ulong new_ccr)
2549 PUT_CCR(env, new_ccr);
2552 // CWP handling is reversed in V9, but we still use the V8 register
2554 target_ulong helper_rdcwp(void)
2556 return GET_CWP64(env);
2559 void helper_wrcwp(target_ulong new_cwp)
2561 PUT_CWP64(env, new_cwp);
2564 // This function uses non-native bit order
2565 #define GET_FIELD(X, FROM, TO) \
2566 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
2568 // This function uses the order in the manuals, i.e. bit 0 is 2^0
2569 #define GET_FIELD_SP(X, FROM, TO) \
2570 GET_FIELD(X, 63 - (TO), 63 - (FROM))
2572 target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
2574 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
2575 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
2576 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
2577 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
2578 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
2579 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
2580 (((pixel_addr >> 55) & 1) << 4) |
2581 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
2582 GET_FIELD_SP(pixel_addr, 11, 12);
2585 target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
2589 tmp = addr + offset;
2591 env->gsr |= tmp & 7ULL;
2595 target_ulong helper_popc(target_ulong val)
2597 return ctpop64(val);
2600 static inline uint64_t *get_gregset(uint64_t pstate)
2615 static inline void change_pstate(uint64_t new_pstate)
2617 uint64_t pstate_regs, new_pstate_regs;
2618 uint64_t *src, *dst;
2620 pstate_regs = env->pstate & 0xc01;
2621 new_pstate_regs = new_pstate & 0xc01;
2622 if (new_pstate_regs != pstate_regs) {
2623 // Switch global register bank
2624 src = get_gregset(new_pstate_regs);
2625 dst = get_gregset(pstate_regs);
2626 memcpy32(dst, env->gregs);
2627 memcpy32(env->gregs, src);
2629 env->pstate = new_pstate;
2632 void helper_wrpstate(target_ulong new_state)
2634 if (!(env->def->features & CPU_FEATURE_GL))
2635 change_pstate(new_state & 0xf3f);
2638 void helper_done(void)
2640 env->pc = env->tsptr->tpc;
2641 env->npc = env->tsptr->tnpc + 4;
2642 PUT_CCR(env, env->tsptr->tstate >> 32);
2643 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2644 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2645 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2647 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2650 void helper_retry(void)
2652 env->pc = env->tsptr->tpc;
2653 env->npc = env->tsptr->tnpc;
2654 PUT_CCR(env, env->tsptr->tstate >> 32);
2655 env->asi = (env->tsptr->tstate >> 24) & 0xff;
2656 change_pstate((env->tsptr->tstate >> 8) & 0xf3f);
2657 PUT_CWP64(env, env->tsptr->tstate & 0xff);
2659 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2662 void helper_set_softint(uint64_t value)
2664 env->softint |= (uint32_t)value;
2667 void helper_clear_softint(uint64_t value)
2669 env->softint &= (uint32_t)~value;
2672 void helper_write_softint(uint64_t value)
2674 env->softint = (uint32_t)value;
2678 void helper_flush(target_ulong addr)
2681 tb_invalidate_page_range(addr, addr + 8);
2684 #ifdef TARGET_SPARC64
2686 static const char * const excp_names[0x80] = {
2687 [TT_TFAULT] = "Instruction Access Fault",
2688 [TT_TMISS] = "Instruction Access MMU Miss",
2689 [TT_CODE_ACCESS] = "Instruction Access Error",
2690 [TT_ILL_INSN] = "Illegal Instruction",
2691 [TT_PRIV_INSN] = "Privileged Instruction",
2692 [TT_NFPU_INSN] = "FPU Disabled",
2693 [TT_FP_EXCP] = "FPU Exception",
2694 [TT_TOVF] = "Tag Overflow",
2695 [TT_CLRWIN] = "Clean Windows",
2696 [TT_DIV_ZERO] = "Division By Zero",
2697 [TT_DFAULT] = "Data Access Fault",
2698 [TT_DMISS] = "Data Access MMU Miss",
2699 [TT_DATA_ACCESS] = "Data Access Error",
2700 [TT_DPROT] = "Data Protection Error",
2701 [TT_UNALIGNED] = "Unaligned Memory Access",
2702 [TT_PRIV_ACT] = "Privileged Action",
2703 [TT_EXTINT | 0x1] = "External Interrupt 1",
2704 [TT_EXTINT | 0x2] = "External Interrupt 2",
2705 [TT_EXTINT | 0x3] = "External Interrupt 3",
2706 [TT_EXTINT | 0x4] = "External Interrupt 4",
2707 [TT_EXTINT | 0x5] = "External Interrupt 5",
2708 [TT_EXTINT | 0x6] = "External Interrupt 6",
2709 [TT_EXTINT | 0x7] = "External Interrupt 7",
2710 [TT_EXTINT | 0x8] = "External Interrupt 8",
2711 [TT_EXTINT | 0x9] = "External Interrupt 9",
2712 [TT_EXTINT | 0xa] = "External Interrupt 10",
2713 [TT_EXTINT | 0xb] = "External Interrupt 11",
2714 [TT_EXTINT | 0xc] = "External Interrupt 12",
2715 [TT_EXTINT | 0xd] = "External Interrupt 13",
2716 [TT_EXTINT | 0xe] = "External Interrupt 14",
2717 [TT_EXTINT | 0xf] = "External Interrupt 15",
2721 void do_interrupt(CPUState *env)
2723 int intno = env->exception_index;
2726 if (loglevel & CPU_LOG_INT) {
2730 if (intno < 0 || intno >= 0x180)
2732 else if (intno >= 0x100)
2733 name = "Trap Instruction";
2734 else if (intno >= 0xc0)
2735 name = "Window Fill";
2736 else if (intno >= 0x80)
2737 name = "Window Spill";
2739 name = excp_names[intno];
2744 fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
2745 " SP=%016" PRIx64 "\n",
2748 env->npc, env->regwptr[6]);
2749 cpu_dump_state(env, logfile, fprintf, 0);
2755 fprintf(logfile, " code=");
2756 ptr = (uint8_t *)env->pc;
2757 for(i = 0; i < 16; i++) {
2758 fprintf(logfile, " %02x", ldub(ptr + i));
2760 fprintf(logfile, "\n");
2766 #if !defined(CONFIG_USER_ONLY)
2767 if (env->tl >= env->maxtl) {
2768 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
2769 " Error state", env->exception_index, env->tl, env->maxtl);
2773 if (env->tl < env->maxtl - 1) {
2776 env->pstate |= PS_RED;
2777 if (env->tl < env->maxtl)
2780 env->tsptr = &env->ts[env->tl & MAXTL_MASK];
2781 env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
2782 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
2784 env->tsptr->tpc = env->pc;
2785 env->tsptr->tnpc = env->npc;
2786 env->tsptr->tt = intno;
2787 if (!(env->def->features & CPU_FEATURE_GL)) {
2790 change_pstate(PS_PEF | PS_PRIV | PS_IG);
2797 change_pstate(PS_PEF | PS_PRIV | PS_MG);
2800 change_pstate(PS_PEF | PS_PRIV | PS_AG);
2804 if (intno == TT_CLRWIN)
2805 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
2806 else if ((intno & 0x1c0) == TT_SPILL)
2807 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
2808 else if ((intno & 0x1c0) == TT_FILL)
2809 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
2810 env->tbr &= ~0x7fffULL;
2811 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
2813 env->npc = env->pc + 4;
2814 env->exception_index = 0;
2818 static const char * const excp_names[0x80] = {
2819 [TT_TFAULT] = "Instruction Access Fault",
2820 [TT_ILL_INSN] = "Illegal Instruction",
2821 [TT_PRIV_INSN] = "Privileged Instruction",
2822 [TT_NFPU_INSN] = "FPU Disabled",
2823 [TT_WIN_OVF] = "Window Overflow",
2824 [TT_WIN_UNF] = "Window Underflow",
2825 [TT_UNALIGNED] = "Unaligned Memory Access",
2826 [TT_FP_EXCP] = "FPU Exception",
2827 [TT_DFAULT] = "Data Access Fault",
2828 [TT_TOVF] = "Tag Overflow",
2829 [TT_EXTINT | 0x1] = "External Interrupt 1",
2830 [TT_EXTINT | 0x2] = "External Interrupt 2",
2831 [TT_EXTINT | 0x3] = "External Interrupt 3",
2832 [TT_EXTINT | 0x4] = "External Interrupt 4",
2833 [TT_EXTINT | 0x5] = "External Interrupt 5",
2834 [TT_EXTINT | 0x6] = "External Interrupt 6",
2835 [TT_EXTINT | 0x7] = "External Interrupt 7",
2836 [TT_EXTINT | 0x8] = "External Interrupt 8",
2837 [TT_EXTINT | 0x9] = "External Interrupt 9",
2838 [TT_EXTINT | 0xa] = "External Interrupt 10",
2839 [TT_EXTINT | 0xb] = "External Interrupt 11",
2840 [TT_EXTINT | 0xc] = "External Interrupt 12",
2841 [TT_EXTINT | 0xd] = "External Interrupt 13",
2842 [TT_EXTINT | 0xe] = "External Interrupt 14",
2843 [TT_EXTINT | 0xf] = "External Interrupt 15",
2844 [TT_TOVF] = "Tag Overflow",
2845 [TT_CODE_ACCESS] = "Instruction Access Error",
2846 [TT_DATA_ACCESS] = "Data Access Error",
2847 [TT_DIV_ZERO] = "Division By Zero",
2848 [TT_NCP_INSN] = "Coprocessor Disabled",
2852 void do_interrupt(CPUState *env)
2854 int cwp, intno = env->exception_index;
2857 if (loglevel & CPU_LOG_INT) {
2861 if (intno < 0 || intno >= 0x100)
2863 else if (intno >= 0x80)
2864 name = "Trap Instruction";
2866 name = excp_names[intno];
2871 fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
2874 env->npc, env->regwptr[6]);
2875 cpu_dump_state(env, logfile, fprintf, 0);
2881 fprintf(logfile, " code=");
2882 ptr = (uint8_t *)env->pc;
2883 for(i = 0; i < 16; i++) {
2884 fprintf(logfile, " %02x", ldub(ptr + i));
2886 fprintf(logfile, "\n");
2892 #if !defined(CONFIG_USER_ONLY)
2893 if (env->psret == 0) {
2894 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
2895 env->exception_index);
2900 cwp = cpu_cwp_dec(env, env->cwp - 1);
2901 cpu_set_cwp(env, cwp);
2902 env->regwptr[9] = env->pc;
2903 env->regwptr[10] = env->npc;
2904 env->psrps = env->psrs;
2906 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
2908 env->npc = env->pc + 4;
2909 env->exception_index = 0;
2913 #if !defined(CONFIG_USER_ONLY)
2915 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2918 #define MMUSUFFIX _mmu
2919 #define ALIGNED_ONLY
2922 #include "softmmu_template.h"
2925 #include "softmmu_template.h"
2928 #include "softmmu_template.h"
2931 #include "softmmu_template.h"
2933 /* XXX: make it generic ? */
2934 static void cpu_restore_state2(void *retaddr)
2936 TranslationBlock *tb;
2940 /* now we have a real cpu fault */
2941 pc = (unsigned long)retaddr;
2942 tb = tb_find_pc(pc);
2944 /* the PC is inside the translated code. It means that we have
2945 a virtual CPU fault */
2946 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
2951 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
2954 #ifdef DEBUG_UNALIGNED
2955 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2956 "\n", addr, env->pc);
2958 cpu_restore_state2(retaddr);
2959 raise_exception(TT_UNALIGNED);
2962 /* try to fill the TLB and return an exception if error. If retaddr is
2963 NULL, it means that the function was called in C code (i.e. not
2964 from generated code or from helper.c) */
2965 /* XXX: fix it to restore all registers */
2966 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2969 CPUState *saved_env;
2971 /* XXX: hack to restore env in all cases, even if not called from
2974 env = cpu_single_env;
2976 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2978 cpu_restore_state2(retaddr);
2986 #ifndef TARGET_SPARC64
2987 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
2990 CPUState *saved_env;
2992 /* XXX: hack to restore env in all cases, even if not called from
2995 env = cpu_single_env;
2996 #ifdef DEBUG_UNASSIGNED
2998 printf("Unassigned mem %s access to " TARGET_FMT_plx
2999 " asi 0x%02x from " TARGET_FMT_lx "\n",
3000 is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
3003 printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
3005 is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
3007 if (env->mmuregs[3]) /* Fault status register */
3008 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
3010 env->mmuregs[3] |= 1 << 16;
3012 env->mmuregs[3] |= 1 << 5;
3014 env->mmuregs[3] |= 1 << 6;
3016 env->mmuregs[3] |= 1 << 7;
3017 env->mmuregs[3] |= (5 << 2) | 2;
3018 env->mmuregs[4] = addr; /* Fault address register */
3019 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
3021 raise_exception(TT_CODE_ACCESS);
3023 raise_exception(TT_DATA_ACCESS);
3028 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
3031 #ifdef DEBUG_UNASSIGNED
3032 CPUState *saved_env;
3034 /* XXX: hack to restore env in all cases, even if not called from
3037 env = cpu_single_env;
3038 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
3039 "\n", addr, env->pc);
3043 raise_exception(TT_CODE_ACCESS);
3045 raise_exception(TT_DATA_ACCESS);