2 #include "host-utils.h"
7 //#define DEBUG_UNALIGNED
8 //#define DEBUG_UNASSIGNED
11 #define DPRINTF_MMU(fmt, args...) \
12 do { printf("MMU: " fmt , ##args); } while (0)
14 #define DPRINTF_MMU(fmt, args...)
18 #define DPRINTF_MXCC(fmt, args...) \
19 do { printf("MXCC: " fmt , ##args); } while (0)
21 #define DPRINTF_MXCC(fmt, args...)
24 void raise_exception(int tt)
26 env->exception_index = tt;
30 void check_ieee_exceptions()
32 T0 = get_float_exception_flags(&env->fp_status);
35 /* Copy IEEE 754 flags into FSR */
36 if (T0 & float_flag_invalid)
38 if (T0 & float_flag_overflow)
40 if (T0 & float_flag_underflow)
42 if (T0 & float_flag_divbyzero)
44 if (T0 & float_flag_inexact)
47 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
49 /* Unmasked exception, generate a trap */
50 env->fsr |= FSR_FTT_IEEE_EXCP;
51 raise_exception(TT_FP_EXCP);
55 /* Accumulate exceptions */
56 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
61 #ifdef USE_INT_TO_FLOAT_HELPERS
64 set_float_exception_flags(0, &env->fp_status);
65 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
66 check_ieee_exceptions();
71 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
76 set_float_exception_flags(0, &env->fp_status);
77 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
78 check_ieee_exceptions();
83 set_float_exception_flags(0, &env->fp_status);
84 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
85 check_ieee_exceptions();
92 FT0 = float32_abs(FT1);
98 DT0 = float64_abs(DT1);
104 set_float_exception_flags(0, &env->fp_status);
105 FT0 = float32_sqrt(FT1, &env->fp_status);
106 check_ieee_exceptions();
111 set_float_exception_flags(0, &env->fp_status);
112 DT0 = float64_sqrt(DT1, &env->fp_status);
113 check_ieee_exceptions();
116 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
117 void glue(do_, name) (void) \
119 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
120 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
121 case float_relation_unordered: \
122 T0 = (FSR_FCC1 | FSR_FCC0) << FS; \
123 if ((env->fsr & FSR_NVM) || TRAP) { \
125 env->fsr |= FSR_NVC; \
126 env->fsr |= FSR_FTT_IEEE_EXCP; \
127 raise_exception(TT_FP_EXCP); \
129 env->fsr |= FSR_NVA; \
132 case float_relation_less: \
133 T0 = FSR_FCC0 << FS; \
135 case float_relation_greater: \
136 T0 = FSR_FCC1 << FS; \
145 GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
146 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
148 GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
149 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
151 #ifdef TARGET_SPARC64
152 GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
153 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
155 GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
156 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
158 GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
159 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
161 GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
162 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
164 GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
165 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
167 GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
168 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
171 #ifndef TARGET_SPARC64
172 #ifndef CONFIG_USER_ONLY
175 static void dump_mxcc(CPUState *env)
177 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
178 env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
179 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
180 " %016llx %016llx %016llx %016llx\n",
181 env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
182 env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
186 void helper_ld_asi(int asi, int size, int sign)
191 uint32_t last_T0 = T0;
195 case 2: /* SuperSparc MXCC registers */
197 case 0x01c00a00: /* MXCC control register */
199 ret = env->mxccregs[3];
200 T0 = env->mxccregs[3] >> 32;
202 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
204 case 0x01c00a04: /* MXCC control register */
206 ret = env->mxccregs[3];
208 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
210 case 0x01c00c00: /* Module reset register */
212 ret = env->mxccregs[5] >> 32;
213 T0 = env->mxccregs[5];
214 // should we do something here?
216 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
218 case 0x01c00f00: /* MBus port address register */
220 ret = env->mxccregs[7];
221 T0 = env->mxccregs[7] >> 32;
223 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
226 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
229 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"
230 "T0 = %08x\n", asi, size, sign, last_T0, ret, T0);
235 case 3: /* MMU probe */
239 mmulev = (T0 >> 8) & 15;
243 ret = mmu_probe(env, T0, mmulev);
246 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
249 case 4: /* read MMU regs */
251 int reg = (T0 >> 8) & 0xf;
253 ret = env->mmuregs[reg];
254 if (reg == 3) /* Fault status cleared on read */
255 env->mmuregs[reg] = 0;
256 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
259 case 9: /* Supervisor code access */
265 ret = lduw_code(T0 & ~1);
269 ret = ldl_code(T0 & ~3);
272 tmp = ldq_code(T0 & ~7);
278 case 0xa: /* User data access */
284 ret = lduw_user(T0 & ~1);
288 ret = ldl_user(T0 & ~3);
291 tmp = ldq_user(T0 & ~7);
297 case 0xb: /* Supervisor data access */
300 ret = ldub_kernel(T0);
303 ret = lduw_kernel(T0 & ~1);
307 ret = ldl_kernel(T0 & ~3);
310 tmp = ldq_kernel(T0 & ~7);
316 case 0xc: /* I-cache tag */
317 case 0xd: /* I-cache data */
318 case 0xe: /* D-cache tag */
319 case 0xf: /* D-cache data */
321 case 0x20: /* MMU passthrough */
327 ret = lduw_phys(T0 & ~1);
331 ret = ldl_phys(T0 & ~3);
334 tmp = ldq_phys(T0 & ~7);
340 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
341 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
344 ret = ldub_phys((target_phys_addr_t)T0
345 | ((target_phys_addr_t)(asi & 0xf) << 32));
348 ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
349 | ((target_phys_addr_t)(asi & 0xf) << 32));
353 ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
354 | ((target_phys_addr_t)(asi & 0xf) << 32));
357 tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
358 | ((target_phys_addr_t)(asi & 0xf) << 32));
364 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
366 do_unassigned_access(T0, 0, 0, 1);
387 void helper_st_asi(int asi, int size)
390 case 2: /* SuperSparc MXCC registers */
392 case 0x01c00000: /* MXCC stream data register 0 */
394 env->mxccdata[0] = ((uint64_t)T1 << 32) | T2;
396 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
398 case 0x01c00008: /* MXCC stream data register 1 */
400 env->mxccdata[1] = ((uint64_t)T1 << 32) | T2;
402 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
404 case 0x01c00010: /* MXCC stream data register 2 */
406 env->mxccdata[2] = ((uint64_t)T1 << 32) | T2;
408 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
410 case 0x01c00018: /* MXCC stream data register 3 */
412 env->mxccdata[3] = ((uint64_t)T1 << 32) | T2;
414 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
416 case 0x01c00100: /* MXCC stream source */
418 env->mxccregs[0] = ((uint64_t)T1 << 32) | T2;
420 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
421 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
422 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
423 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
424 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
426 case 0x01c00200: /* MXCC stream destination */
428 env->mxccregs[1] = ((uint64_t)T1 << 32) | T2;
430 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
431 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
432 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
433 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
434 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
436 case 0x01c00a00: /* MXCC control register */
438 env->mxccregs[3] = ((uint64_t)T1 << 32) | T2;
440 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
442 case 0x01c00a04: /* MXCC control register */
444 env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | T1;
446 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
448 case 0x01c00e00: /* MXCC error register */
449 // writing a 1 bit clears the error
451 env->mxccregs[6] &= ~(((uint64_t)T1 << 32) | T2);
453 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
455 case 0x01c00f00: /* MBus port address register */
457 env->mxccregs[7] = ((uint64_t)T1 << 32) | T2;
459 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
462 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
465 DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1);
470 case 3: /* MMU flush */
474 mmulev = (T0 >> 8) & 15;
475 DPRINTF_MMU("mmu flush level %d\n", mmulev);
477 case 0: // flush page
478 tlb_flush_page(env, T0 & 0xfffff000);
480 case 1: // flush segment (256k)
481 case 2: // flush region (16M)
482 case 3: // flush context (4G)
483 case 4: // flush entire
494 case 4: /* write MMU regs */
496 int reg = (T0 >> 8) & 0xf;
499 oldreg = env->mmuregs[reg];
502 env->mmuregs[reg] &= ~(MMU_E | MMU_NF | env->mmu_bm);
503 env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | env->mmu_bm);
504 // Mappings generated during no-fault mode or MMU
505 // disabled mode are invalid in normal mode
506 if (oldreg != env->mmuregs[reg])
510 env->mmuregs[reg] = T1;
511 if (oldreg != env->mmuregs[reg]) {
512 /* we flush when the MMU context changes because
513 QEMU has no MMU context support */
521 env->mmuregs[reg] = T1;
524 if (oldreg != env->mmuregs[reg]) {
525 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
532 case 0xa: /* User data access */
538 stw_user(T0 & ~1, T1);
542 stl_user(T0 & ~3, T1);
545 stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2);
549 case 0xb: /* Supervisor data access */
555 stw_kernel(T0 & ~1, T1);
559 stl_kernel(T0 & ~3, T1);
562 stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2);
566 case 0xc: /* I-cache tag */
567 case 0xd: /* I-cache data */
568 case 0xe: /* D-cache tag */
569 case 0xf: /* D-cache data */
570 case 0x10: /* I/D-cache flush page */
571 case 0x11: /* I/D-cache flush segment */
572 case 0x12: /* I/D-cache flush region */
573 case 0x13: /* I/D-cache flush context */
574 case 0x14: /* I/D-cache flush user */
576 case 0x17: /* Block copy, sta access */
579 // address (T0) = dst
582 uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
584 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
585 temp = ldl_kernel(src);
586 stl_kernel(dst, temp);
590 case 0x1f: /* Block fill, stda access */
593 // address (T0) = dst
596 uint32_t dst = T0 & 7;
599 val = (((uint64_t)T1) << 32) | T2;
601 for (i = 0; i < 32; i += 8, dst += 8)
602 stq_kernel(dst, val);
605 case 0x20: /* MMU passthrough */
612 stw_phys(T0 & ~1, T1);
616 stl_phys(T0 & ~3, T1);
619 stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2);
624 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
625 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
629 stb_phys((target_phys_addr_t)T0
630 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
633 stw_phys((target_phys_addr_t)(T0 & ~1)
634 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
638 stl_phys((target_phys_addr_t)(T0 & ~3)
639 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
642 stq_phys((target_phys_addr_t)(T0 & ~7)
643 | ((target_phys_addr_t)(asi & 0xf) << 32),
644 ((uint64_t)T1 << 32) | T2);
649 case 0x31: /* Ross RT620 I-cache flush */
650 case 0x36: /* I-cache flash clear */
651 case 0x37: /* D-cache flash clear */
653 case 9: /* Supervisor code access, XXX */
654 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
656 do_unassigned_access(T0, 1, 0, 1);
661 #endif /* CONFIG_USER_ONLY */
662 #else /* TARGET_SPARC64 */
664 #ifdef CONFIG_USER_ONLY
665 void helper_ld_asi(int asi, int size, int sign)
670 raise_exception(TT_PRIV_ACT);
673 case 0x80: // Primary
674 case 0x82: // Primary no-fault
675 case 0x88: // Primary LE
676 case 0x8a: // Primary no-fault LE
683 ret = lduw_raw(T0 & ~1);
686 ret = ldl_raw(T0 & ~3);
690 ret = ldq_raw(T0 & ~7);
695 case 0x81: // Secondary
696 case 0x83: // Secondary no-fault
697 case 0x89: // Secondary LE
698 case 0x8b: // Secondary no-fault LE
705 /* Convert from little endian */
707 case 0x88: // Primary LE
708 case 0x89: // Secondary LE
709 case 0x8a: // Primary no-fault LE
710 case 0x8b: // Secondary no-fault LE
728 /* Convert to signed number */
747 void helper_st_asi(int asi, int size)
750 raise_exception(TT_PRIV_ACT);
752 /* Convert to little endian */
754 case 0x88: // Primary LE
755 case 0x89: // Secondary LE
774 case 0x80: // Primary
775 case 0x88: // Primary LE
782 stw_raw(T0 & ~1, T1);
785 stl_raw(T0 & ~3, T1);
789 stq_raw(T0 & ~7, T1);
794 case 0x81: // Secondary
795 case 0x89: // Secondary LE
799 case 0x82: // Primary no-fault, RO
800 case 0x83: // Secondary no-fault, RO
801 case 0x8a: // Primary no-fault LE, RO
802 case 0x8b: // Secondary no-fault LE, RO
804 do_unassigned_access(T0, 1, 0, 1);
809 #else /* CONFIG_USER_ONLY */
811 void helper_ld_asi(int asi, int size, int sign)
815 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
816 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
817 raise_exception(TT_PRIV_ACT);
820 case 0x10: // As if user primary
821 case 0x18: // As if user primary LE
822 case 0x80: // Primary
823 case 0x82: // Primary no-fault
824 case 0x88: // Primary LE
825 case 0x8a: // Primary no-fault LE
826 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
827 if (env->hpstate & HS_PRIV) {
833 ret = lduw_hypv(T0 & ~1);
836 ret = ldl_hypv(T0 & ~3);
840 ret = ldq_hypv(T0 & ~7);
846 ret = ldub_kernel(T0);
849 ret = lduw_kernel(T0 & ~1);
852 ret = ldl_kernel(T0 & ~3);
856 ret = ldq_kernel(T0 & ~7);
866 ret = lduw_user(T0 & ~1);
869 ret = ldl_user(T0 & ~3);
873 ret = ldq_user(T0 & ~7);
879 case 0x15: // Bypass, non-cacheable
880 case 0x1c: // Bypass LE
881 case 0x1d: // Bypass, non-cacheable LE
888 ret = lduw_phys(T0 & ~1);
891 ret = ldl_phys(T0 & ~3);
895 ret = ldq_phys(T0 & ~7);
900 case 0x04: // Nucleus
901 case 0x0c: // Nucleus Little Endian (LE)
902 case 0x11: // As if user secondary
903 case 0x19: // As if user secondary LE
904 case 0x24: // Nucleus quad LDD 128 bit atomic
905 case 0x2c: // Nucleus quad LDD 128 bit atomic
906 case 0x4a: // UPA config
907 case 0x81: // Secondary
908 case 0x83: // Secondary no-fault
909 case 0x89: // Secondary LE
910 case 0x8b: // Secondary no-fault LE
916 case 0x50: // I-MMU regs
918 int reg = (T0 >> 3) & 0xf;
920 ret = env->immuregs[reg];
923 case 0x51: // I-MMU 8k TSB pointer
924 case 0x52: // I-MMU 64k TSB pointer
925 case 0x55: // I-MMU data access
928 case 0x56: // I-MMU tag read
932 for (i = 0; i < 64; i++) {
933 // Valid, ctx match, vaddr match
934 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
935 env->itlb_tag[i] == T0) {
936 ret = env->itlb_tag[i];
942 case 0x58: // D-MMU regs
944 int reg = (T0 >> 3) & 0xf;
946 ret = env->dmmuregs[reg];
949 case 0x5e: // D-MMU tag read
953 for (i = 0; i < 64; i++) {
954 // Valid, ctx match, vaddr match
955 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
956 env->dtlb_tag[i] == T0) {
957 ret = env->dtlb_tag[i];
963 case 0x59: // D-MMU 8k TSB pointer
964 case 0x5a: // D-MMU 64k TSB pointer
965 case 0x5b: // D-MMU data pointer
966 case 0x5d: // D-MMU data access
967 case 0x48: // Interrupt dispatch, RO
968 case 0x49: // Interrupt data receive
969 case 0x7f: // Incoming interrupt vector, RO
972 case 0x54: // I-MMU data in, WO
973 case 0x57: // I-MMU demap, WO
974 case 0x5c: // D-MMU data in, WO
975 case 0x5f: // D-MMU demap, WO
976 case 0x77: // Interrupt vector, WO
978 do_unassigned_access(T0, 0, 0, 1);
983 /* Convert from little endian */
985 case 0x0c: // Nucleus Little Endian (LE)
986 case 0x18: // As if user primary LE
987 case 0x19: // As if user secondary LE
988 case 0x1c: // Bypass LE
989 case 0x1d: // Bypass, non-cacheable LE
990 case 0x88: // Primary LE
991 case 0x89: // Secondary LE
992 case 0x8a: // Primary no-fault LE
993 case 0x8b: // Secondary no-fault LE
1011 /* Convert to signed number */
1018 ret = (int16_t) ret;
1021 ret = (int32_t) ret;
1030 void helper_st_asi(int asi, int size)
1032 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1033 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
1034 raise_exception(TT_PRIV_ACT);
1036 /* Convert to little endian */
1038 case 0x0c: // Nucleus Little Endian (LE)
1039 case 0x18: // As if user primary LE
1040 case 0x19: // As if user secondary LE
1041 case 0x1c: // Bypass LE
1042 case 0x1d: // Bypass, non-cacheable LE
1043 case 0x88: // Primary LE
1044 case 0x89: // Secondary LE
1063 case 0x10: // As if user primary
1064 case 0x18: // As if user primary LE
1065 case 0x80: // Primary
1066 case 0x88: // Primary LE
1067 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1068 if (env->hpstate & HS_PRIV) {
1074 stw_hypv(T0 & ~1, T1);
1077 stl_hypv(T0 & ~3, T1);
1081 stq_hypv(T0 & ~7, T1);
1090 stw_kernel(T0 & ~1, T1);
1093 stl_kernel(T0 & ~3, T1);
1097 stq_kernel(T0 & ~7, T1);
1107 stw_user(T0 & ~1, T1);
1110 stl_user(T0 & ~3, T1);
1114 stq_user(T0 & ~7, T1);
1119 case 0x14: // Bypass
1120 case 0x15: // Bypass, non-cacheable
1121 case 0x1c: // Bypass LE
1122 case 0x1d: // Bypass, non-cacheable LE
1129 stw_phys(T0 & ~1, T1);
1132 stl_phys(T0 & ~3, T1);
1136 stq_phys(T0 & ~7, T1);
1141 case 0x04: // Nucleus
1142 case 0x0c: // Nucleus Little Endian (LE)
1143 case 0x11: // As if user secondary
1144 case 0x19: // As if user secondary LE
1145 case 0x24: // Nucleus quad LDD 128 bit atomic
1146 case 0x2c: // Nucleus quad LDD 128 bit atomic
1147 case 0x4a: // UPA config
1148 case 0x81: // Secondary
1149 case 0x89: // Secondary LE
1157 env->lsu = T1 & (DMMU_E | IMMU_E);
1158 // Mappings generated during D/I MMU disabled mode are
1159 // invalid in normal mode
1160 if (oldreg != env->lsu) {
1161 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
1169 case 0x50: // I-MMU regs
1171 int reg = (T0 >> 3) & 0xf;
1174 oldreg = env->immuregs[reg];
1179 case 1: // Not in I-MMU
1186 T1 = 0; // Clear SFSR
1188 case 5: // TSB access
1189 case 6: // Tag access
1193 env->immuregs[reg] = T1;
1194 if (oldreg != env->immuregs[reg]) {
1195 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1202 case 0x54: // I-MMU data in
1206 // Try finding an invalid entry
1207 for (i = 0; i < 64; i++) {
1208 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1209 env->itlb_tag[i] = env->immuregs[6];
1210 env->itlb_tte[i] = T1;
1214 // Try finding an unlocked entry
1215 for (i = 0; i < 64; i++) {
1216 if ((env->itlb_tte[i] & 0x40) == 0) {
1217 env->itlb_tag[i] = env->immuregs[6];
1218 env->itlb_tte[i] = T1;
1225 case 0x55: // I-MMU data access
1227 unsigned int i = (T0 >> 3) & 0x3f;
1229 env->itlb_tag[i] = env->immuregs[6];
1230 env->itlb_tte[i] = T1;
1233 case 0x57: // I-MMU demap
1236 case 0x58: // D-MMU regs
1238 int reg = (T0 >> 3) & 0xf;
1241 oldreg = env->dmmuregs[reg];
1247 if ((T1 & 1) == 0) {
1248 T1 = 0; // Clear SFSR, Fault address
1249 env->dmmuregs[4] = 0;
1251 env->dmmuregs[reg] = T1;
1253 case 1: // Primary context
1254 case 2: // Secondary context
1255 case 5: // TSB access
1256 case 6: // Tag access
1257 case 7: // Virtual Watchpoint
1258 case 8: // Physical Watchpoint
1262 env->dmmuregs[reg] = T1;
1263 if (oldreg != env->dmmuregs[reg]) {
1264 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1271 case 0x5c: // D-MMU data in
1275 // Try finding an invalid entry
1276 for (i = 0; i < 64; i++) {
1277 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1278 env->dtlb_tag[i] = env->dmmuregs[6];
1279 env->dtlb_tte[i] = T1;
1283 // Try finding an unlocked entry
1284 for (i = 0; i < 64; i++) {
1285 if ((env->dtlb_tte[i] & 0x40) == 0) {
1286 env->dtlb_tag[i] = env->dmmuregs[6];
1287 env->dtlb_tte[i] = T1;
1294 case 0x5d: // D-MMU data access
1296 unsigned int i = (T0 >> 3) & 0x3f;
1298 env->dtlb_tag[i] = env->dmmuregs[6];
1299 env->dtlb_tte[i] = T1;
1302 case 0x5f: // D-MMU demap
1303 case 0x49: // Interrupt data receive
1306 case 0x51: // I-MMU 8k TSB pointer, RO
1307 case 0x52: // I-MMU 64k TSB pointer, RO
1308 case 0x56: // I-MMU tag read, RO
1309 case 0x59: // D-MMU 8k TSB pointer, RO
1310 case 0x5a: // D-MMU 64k TSB pointer, RO
1311 case 0x5b: // D-MMU data pointer, RO
1312 case 0x5e: // D-MMU tag read, RO
1313 case 0x48: // Interrupt dispatch, RO
1314 case 0x7f: // Incoming interrupt vector, RO
1315 case 0x82: // Primary no-fault, RO
1316 case 0x83: // Secondary no-fault, RO
1317 case 0x8a: // Primary no-fault LE, RO
1318 case 0x8b: // Secondary no-fault LE, RO
1320 do_unassigned_access(T0, 1, 0, 1);
1324 #endif /* CONFIG_USER_ONLY */
1326 void helper_ldf_asi(int asi, int size, int rd)
1328 target_ulong tmp_T0 = T0, tmp_T1 = T1;
1332 case 0xf0: // Block load primary
1333 case 0xf1: // Block load secondary
1334 case 0xf8: // Block load primary LE
1335 case 0xf9: // Block load secondary LE
1337 raise_exception(TT_ILL_INSN);
1341 raise_exception(TT_UNALIGNED);
1344 for (i = 0; i < 16; i++) {
1345 helper_ld_asi(asi & 0x8f, 4, 0);
1346 *(uint32_t *)&env->fpr[rd++] = T1;
1357 helper_ld_asi(asi, size, 0);
1361 *((uint32_t *)&FT0) = T1;
1364 *((int64_t *)&DT0) = T1;
1370 void helper_stf_asi(int asi, int size, int rd)
1372 target_ulong tmp_T0 = T0, tmp_T1 = T1;
1376 case 0xf0: // Block store primary
1377 case 0xf1: // Block store secondary
1378 case 0xf8: // Block store primary LE
1379 case 0xf9: // Block store secondary LE
1381 raise_exception(TT_ILL_INSN);
1385 raise_exception(TT_UNALIGNED);
1388 for (i = 0; i < 16; i++) {
1389 T1 = *(uint32_t *)&env->fpr[rd++];
1390 helper_st_asi(asi & 0x8f, 4);
1404 T1 = *((uint32_t *)&FT0);
1407 T1 = *((int64_t *)&DT0);
1410 helper_st_asi(asi, size);
1414 #endif /* TARGET_SPARC64 */
1416 #ifndef TARGET_SPARC64
1421 if (env->psret == 1)
1422 raise_exception(TT_ILL_INSN);
1425 cwp = (env->cwp + 1) & (NWINDOWS - 1);
1426 if (env->wim & (1 << cwp)) {
1427 raise_exception(TT_WIN_UNF);
1430 env->psrs = env->psrps;
1434 void helper_ldfsr(void)
1437 switch (env->fsr & FSR_RD_MASK) {
1438 case FSR_RD_NEAREST:
1439 rnd_mode = float_round_nearest_even;
1443 rnd_mode = float_round_to_zero;
1446 rnd_mode = float_round_up;
1449 rnd_mode = float_round_down;
1452 set_float_rounding_mode(rnd_mode, &env->fp_status);
1457 env->exception_index = EXCP_DEBUG;
1461 #ifndef TARGET_SPARC64
1464 if ((T0 & PSR_CWP) >= NWINDOWS)
1465 raise_exception(TT_ILL_INSN);
1482 static inline uint64_t *get_gregset(uint64_t pstate)
1497 static inline void change_pstate(uint64_t new_pstate)
1499 uint64_t pstate_regs, new_pstate_regs;
1500 uint64_t *src, *dst;
1502 pstate_regs = env->pstate & 0xc01;
1503 new_pstate_regs = new_pstate & 0xc01;
1504 if (new_pstate_regs != pstate_regs) {
1505 // Switch global register bank
1506 src = get_gregset(new_pstate_regs);
1507 dst = get_gregset(pstate_regs);
1508 memcpy32(dst, env->gregs);
1509 memcpy32(env->gregs, src);
1511 env->pstate = new_pstate;
1514 void do_wrpstate(void)
1516 change_pstate(T0 & 0xf3f);
1522 env->pc = env->tnpc[env->tl];
1523 env->npc = env->tnpc[env->tl] + 4;
1524 PUT_CCR(env, env->tstate[env->tl] >> 32);
1525 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
1526 change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
1527 PUT_CWP64(env, env->tstate[env->tl] & 0xff);
1533 env->pc = env->tpc[env->tl];
1534 env->npc = env->tnpc[env->tl];
1535 PUT_CCR(env, env->tstate[env->tl] >> 32);
1536 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
1537 change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
1538 PUT_CWP64(env, env->tstate[env->tl] & 0xff);
1542 void set_cwp(int new_cwp)
1544 /* put the modified wrap registers at their proper location */
1545 if (env->cwp == (NWINDOWS - 1))
1546 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
1548 /* put the wrap registers at their temporary location */
1549 if (new_cwp == (NWINDOWS - 1))
1550 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
1551 env->regwptr = env->regbase + (new_cwp * 16);
1552 REGWPTR = env->regwptr;
1555 void cpu_set_cwp(CPUState *env1, int new_cwp)
1557 CPUState *saved_env;
1559 target_ulong *saved_regwptr;
1564 saved_regwptr = REGWPTR;
1570 REGWPTR = saved_regwptr;
1574 #ifdef TARGET_SPARC64
1575 void do_interrupt(int intno)
1578 if (loglevel & CPU_LOG_INT) {
1580 fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
1583 env->npc, env->regwptr[6]);
1584 cpu_dump_state(env, logfile, fprintf, 0);
1590 fprintf(logfile, " code=");
1591 ptr = (uint8_t *)env->pc;
1592 for(i = 0; i < 16; i++) {
1593 fprintf(logfile, " %02x", ldub(ptr + i));
1595 fprintf(logfile, "\n");
1601 #if !defined(CONFIG_USER_ONLY)
1602 if (env->tl == MAXTL) {
1603 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
1607 env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
1608 ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
1609 env->tpc[env->tl] = env->pc;
1610 env->tnpc[env->tl] = env->npc;
1611 env->tt[env->tl] = intno;
1612 change_pstate(PS_PEF | PS_PRIV | PS_AG);
1614 if (intno == TT_CLRWIN)
1615 set_cwp((env->cwp - 1) & (NWINDOWS - 1));
1616 else if ((intno & 0x1c0) == TT_SPILL)
1617 set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
1618 else if ((intno & 0x1c0) == TT_FILL)
1619 set_cwp((env->cwp + 1) & (NWINDOWS - 1));
1620 env->tbr &= ~0x7fffULL;
1621 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
1622 if (env->tl < MAXTL - 1) {
1625 env->pstate |= PS_RED;
1626 if (env->tl != MAXTL)
1630 env->npc = env->pc + 4;
1631 env->exception_index = 0;
1634 void do_interrupt(int intno)
1639 if (loglevel & CPU_LOG_INT) {
1641 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
1644 env->npc, env->regwptr[6]);
1645 cpu_dump_state(env, logfile, fprintf, 0);
1651 fprintf(logfile, " code=");
1652 ptr = (uint8_t *)env->pc;
1653 for(i = 0; i < 16; i++) {
1654 fprintf(logfile, " %02x", ldub(ptr + i));
1656 fprintf(logfile, "\n");
1662 #if !defined(CONFIG_USER_ONLY)
1663 if (env->psret == 0) {
1664 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
1669 cwp = (env->cwp - 1) & (NWINDOWS - 1);
1671 env->regwptr[9] = env->pc;
1672 env->regwptr[10] = env->npc;
1673 env->psrps = env->psrs;
1675 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
1677 env->npc = env->pc + 4;
1678 env->exception_index = 0;
1682 #if !defined(CONFIG_USER_ONLY)
1684 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1687 #define MMUSUFFIX _mmu
1688 #define ALIGNED_ONLY
1690 # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
1692 # define GETPC() (__builtin_return_address(0))
1696 #include "softmmu_template.h"
1699 #include "softmmu_template.h"
1702 #include "softmmu_template.h"
1705 #include "softmmu_template.h"
1707 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1710 #ifdef DEBUG_UNALIGNED
1711 printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
1713 raise_exception(TT_UNALIGNED);
1716 /* try to fill the TLB and return an exception if error. If retaddr is
1717 NULL, it means that the function was called in C code (i.e. not
1718 from generated code or from helper.c) */
1719 /* XXX: fix it to restore all registers */
1720 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1722 TranslationBlock *tb;
1725 CPUState *saved_env;
1727 /* XXX: hack to restore env in all cases, even if not called from
1730 env = cpu_single_env;
1732 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1735 /* now we have a real cpu fault */
1736 pc = (unsigned long)retaddr;
1737 tb = tb_find_pc(pc);
1739 /* the PC is inside the translated code. It means that we have
1740 a virtual CPU fault */
1741 cpu_restore_state(tb, env, pc, (void *)T2);
1751 #ifndef TARGET_SPARC64
1752 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1755 CPUState *saved_env;
1757 /* XXX: hack to restore env in all cases, even if not called from
1760 env = cpu_single_env;
1761 if (env->mmuregs[3]) /* Fault status register */
1762 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
1764 env->mmuregs[3] |= 1 << 16;
1766 env->mmuregs[3] |= 1 << 5;
1768 env->mmuregs[3] |= 1 << 6;
1770 env->mmuregs[3] |= 1 << 7;
1771 env->mmuregs[3] |= (5 << 2) | 2;
1772 env->mmuregs[4] = addr; /* Fault address register */
1773 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1774 #ifdef DEBUG_UNASSIGNED
1775 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
1776 "\n", addr, env->pc);
1779 raise_exception(TT_CODE_ACCESS);
1781 raise_exception(TT_DATA_ACCESS);
1786 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1789 #ifdef DEBUG_UNASSIGNED
1790 CPUState *saved_env;
1792 /* XXX: hack to restore env in all cases, even if not called from
1795 env = cpu_single_env;
1796 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
1801 raise_exception(TT_CODE_ACCESS);
1803 raise_exception(TT_DATA_ACCESS);