4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 #define DYNAMIC_PC 1 /* dynamic pc value */
37 #define JUMP_PC 2 /* dynamic pc value which takes only two values
38 according to jump_pc[T2] */
40 /* global register indexes */
41 static TCGv cpu_env, cpu_regwptr;
42 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
43 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
44 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
48 /* local register indexes (only used inside old micro ops) */
49 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
51 #include "gen-icount.h"
53 typedef struct DisasContext {
54 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
55 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
56 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
60 int address_mask_32bit;
61 struct TranslationBlock *tb;
65 // This function uses non-native bit order
66 #define GET_FIELD(X, FROM, TO) \
67 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
69 // This function uses the order in the manuals, i.e. bit 0 is 2^0
70 #define GET_FIELD_SP(X, FROM, TO) \
71 GET_FIELD(X, 31 - (TO), 31 - (FROM))
73 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
74 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
78 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
79 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
82 #define DFPREG(r) (r & 0x1e)
83 #define QFPREG(r) (r & 0x1c)
86 static int sign_extend(int x, int len)
89 return (x << len) >> len;
92 #define IS_IMM (insn & (1<<13))
94 /* floating point registers moves */
95 static void gen_op_load_fpr_FT0(unsigned int src)
97 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
98 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
101 static void gen_op_load_fpr_FT1(unsigned int src)
103 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
104 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
107 static void gen_op_store_FT0_fpr(unsigned int dst)
109 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
110 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
113 static void gen_op_load_fpr_DT0(unsigned int src)
115 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
116 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
117 offsetof(CPU_DoubleU, l.upper));
118 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
119 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
120 offsetof(CPU_DoubleU, l.lower));
123 static void gen_op_load_fpr_DT1(unsigned int src)
125 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
126 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
127 offsetof(CPU_DoubleU, l.upper));
128 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
129 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
130 offsetof(CPU_DoubleU, l.lower));
133 static void gen_op_store_DT0_fpr(unsigned int dst)
135 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
136 offsetof(CPU_DoubleU, l.upper));
137 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
138 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
139 offsetof(CPU_DoubleU, l.lower));
140 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
143 static void gen_op_load_fpr_QT0(unsigned int src)
145 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
146 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
147 offsetof(CPU_QuadU, l.upmost));
148 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
149 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
150 offsetof(CPU_QuadU, l.upper));
151 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
152 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
153 offsetof(CPU_QuadU, l.lower));
154 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
155 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
156 offsetof(CPU_QuadU, l.lowest));
159 static void gen_op_load_fpr_QT1(unsigned int src)
161 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
162 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
163 offsetof(CPU_QuadU, l.upmost));
164 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
165 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
166 offsetof(CPU_QuadU, l.upper));
167 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
168 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
169 offsetof(CPU_QuadU, l.lower));
170 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
171 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
172 offsetof(CPU_QuadU, l.lowest));
175 static void gen_op_store_QT0_fpr(unsigned int dst)
177 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178 offsetof(CPU_QuadU, l.upmost));
179 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
180 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
181 offsetof(CPU_QuadU, l.upper));
182 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
183 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184 offsetof(CPU_QuadU, l.lower));
185 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
186 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
187 offsetof(CPU_QuadU, l.lowest));
188 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
192 #ifdef CONFIG_USER_ONLY
193 #define supervisor(dc) 0
194 #ifdef TARGET_SPARC64
195 #define hypervisor(dc) 0
198 #define supervisor(dc) (dc->mem_idx >= 1)
199 #ifdef TARGET_SPARC64
200 #define hypervisor(dc) (dc->mem_idx == 2)
205 #ifdef TARGET_SPARC64
207 #define AM_CHECK(dc) ((dc)->address_mask_32bit)
209 #define AM_CHECK(dc) (1)
213 static inline void gen_address_mask(DisasContext *dc, TCGv addr)
215 #ifdef TARGET_SPARC64
217 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
221 static inline void gen_movl_reg_TN(int reg, TCGv tn)
224 tcg_gen_movi_tl(tn, 0);
226 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
228 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
232 static inline void gen_movl_TN_reg(int reg, TCGv tn)
237 tcg_gen_mov_tl(cpu_gregs[reg], tn);
239 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
243 static inline void gen_goto_tb(DisasContext *s, int tb_num,
244 target_ulong pc, target_ulong npc)
246 TranslationBlock *tb;
249 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
250 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
251 /* jump to same page: we can use a direct jump */
252 tcg_gen_goto_tb(tb_num);
253 tcg_gen_movi_tl(cpu_pc, pc);
254 tcg_gen_movi_tl(cpu_npc, npc);
255 tcg_gen_exit_tb((long)tb + tb_num);
257 /* jump to another page: currently not optimized */
258 tcg_gen_movi_tl(cpu_pc, pc);
259 tcg_gen_movi_tl(cpu_npc, npc);
265 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
267 tcg_gen_extu_i32_tl(reg, src);
268 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
269 tcg_gen_andi_tl(reg, reg, 0x1);
272 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
274 tcg_gen_extu_i32_tl(reg, src);
275 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
276 tcg_gen_andi_tl(reg, reg, 0x1);
279 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
281 tcg_gen_extu_i32_tl(reg, src);
282 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
283 tcg_gen_andi_tl(reg, reg, 0x1);
286 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
288 tcg_gen_extu_i32_tl(reg, src);
289 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
290 tcg_gen_andi_tl(reg, reg, 0x1);
293 static inline void gen_cc_clear_icc(void)
295 tcg_gen_movi_i32(cpu_psr, 0);
298 #ifdef TARGET_SPARC64
299 static inline void gen_cc_clear_xcc(void)
301 tcg_gen_movi_i32(cpu_xcc, 0);
307 env->psr |= PSR_ZERO;
308 if ((int32_t) T0 < 0)
311 static inline void gen_cc_NZ_icc(TCGv dst)
316 l1 = gen_new_label();
317 l2 = gen_new_label();
318 r_temp = tcg_temp_new(TCG_TYPE_TL);
319 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
320 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
321 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
323 tcg_gen_ext_i32_tl(r_temp, dst);
324 tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
325 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
327 tcg_temp_free(r_temp);
330 #ifdef TARGET_SPARC64
331 static inline void gen_cc_NZ_xcc(TCGv dst)
335 l1 = gen_new_label();
336 l2 = gen_new_label();
337 tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
338 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
340 tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
341 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
348 env->psr |= PSR_CARRY;
350 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
352 TCGv r_temp1, r_temp2;
355 l1 = gen_new_label();
356 r_temp1 = tcg_temp_new(TCG_TYPE_TL);
357 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
358 tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
359 tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
360 tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
361 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
363 tcg_temp_free(r_temp1);
364 tcg_temp_free(r_temp2);
367 #ifdef TARGET_SPARC64
368 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
372 l1 = gen_new_label();
373 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
374 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
380 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
383 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
387 r_temp = tcg_temp_new(TCG_TYPE_TL);
388 tcg_gen_xor_tl(r_temp, src1, src2);
389 tcg_gen_xori_tl(r_temp, r_temp, -1);
390 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
391 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
392 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
393 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
394 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
395 tcg_temp_free(r_temp);
396 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
399 #ifdef TARGET_SPARC64
400 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
404 r_temp = tcg_temp_new(TCG_TYPE_TL);
405 tcg_gen_xor_tl(r_temp, src1, src2);
406 tcg_gen_xori_tl(r_temp, r_temp, -1);
407 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
408 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
409 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
410 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
411 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
412 tcg_temp_free(r_temp);
413 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
417 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
419 TCGv r_temp, r_const;
422 l1 = gen_new_label();
424 r_temp = tcg_temp_new(TCG_TYPE_TL);
425 tcg_gen_xor_tl(r_temp, src1, src2);
426 tcg_gen_xori_tl(r_temp, r_temp, -1);
427 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
428 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
429 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
430 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
431 r_const = tcg_const_i32(TT_TOVF);
432 tcg_gen_helper_0_1(raise_exception, r_const);
433 tcg_temp_free(r_const);
435 tcg_temp_free(r_temp);
438 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
442 l1 = gen_new_label();
443 tcg_gen_or_tl(cpu_tmp0, src1, src2);
444 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
445 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
446 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
450 static inline void gen_tag_tv(TCGv src1, TCGv src2)
455 l1 = gen_new_label();
456 tcg_gen_or_tl(cpu_tmp0, src1, src2);
457 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
458 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
459 r_const = tcg_const_i32(TT_TOVF);
460 tcg_gen_helper_0_1(raise_exception, r_const);
461 tcg_temp_free(r_const);
465 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
467 tcg_gen_mov_tl(cpu_cc_src, src1);
468 tcg_gen_mov_tl(cpu_cc_src2, src2);
469 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
471 gen_cc_NZ_icc(cpu_cc_dst);
472 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
473 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
474 #ifdef TARGET_SPARC64
476 gen_cc_NZ_xcc(cpu_cc_dst);
477 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
478 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
480 tcg_gen_mov_tl(dst, cpu_cc_dst);
483 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
485 tcg_gen_mov_tl(cpu_cc_src, src1);
486 tcg_gen_mov_tl(cpu_cc_src2, src2);
487 gen_mov_reg_C(cpu_tmp0, cpu_psr);
488 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
490 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
491 #ifdef TARGET_SPARC64
493 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
495 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
496 gen_cc_NZ_icc(cpu_cc_dst);
497 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
498 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
499 #ifdef TARGET_SPARC64
500 gen_cc_NZ_xcc(cpu_cc_dst);
501 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
502 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
504 tcg_gen_mov_tl(dst, cpu_cc_dst);
507 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
509 tcg_gen_mov_tl(cpu_cc_src, src1);
510 tcg_gen_mov_tl(cpu_cc_src2, src2);
511 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
513 gen_cc_NZ_icc(cpu_cc_dst);
514 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
515 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
516 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
517 #ifdef TARGET_SPARC64
519 gen_cc_NZ_xcc(cpu_cc_dst);
520 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
521 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
523 tcg_gen_mov_tl(dst, cpu_cc_dst);
526 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
528 tcg_gen_mov_tl(cpu_cc_src, src1);
529 tcg_gen_mov_tl(cpu_cc_src2, src2);
530 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
531 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
532 gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
534 gen_cc_NZ_icc(cpu_cc_dst);
535 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
536 #ifdef TARGET_SPARC64
538 gen_cc_NZ_xcc(cpu_cc_dst);
539 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
540 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
542 tcg_gen_mov_tl(dst, cpu_cc_dst);
547 env->psr |= PSR_CARRY;
549 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
551 TCGv r_temp1, r_temp2;
554 l1 = gen_new_label();
555 r_temp1 = tcg_temp_new(TCG_TYPE_TL);
556 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
557 tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
558 tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
559 tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
560 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
562 tcg_temp_free(r_temp1);
563 tcg_temp_free(r_temp2);
566 #ifdef TARGET_SPARC64
567 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
571 l1 = gen_new_label();
572 tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
573 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
579 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
582 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
586 r_temp = tcg_temp_new(TCG_TYPE_TL);
587 tcg_gen_xor_tl(r_temp, src1, src2);
588 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
589 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
590 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
591 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
592 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
593 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
594 tcg_temp_free(r_temp);
597 #ifdef TARGET_SPARC64
598 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
602 r_temp = tcg_temp_new(TCG_TYPE_TL);
603 tcg_gen_xor_tl(r_temp, src1, src2);
604 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
605 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
606 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
607 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
608 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
609 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
610 tcg_temp_free(r_temp);
614 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
616 TCGv r_temp, r_const;
619 l1 = gen_new_label();
621 r_temp = tcg_temp_new(TCG_TYPE_TL);
622 tcg_gen_xor_tl(r_temp, src1, src2);
623 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
624 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
625 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
626 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
627 r_const = tcg_const_i32(TT_TOVF);
628 tcg_gen_helper_0_1(raise_exception, r_const);
629 tcg_temp_free(r_const);
631 tcg_temp_free(r_temp);
634 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
636 tcg_gen_mov_tl(cpu_cc_src, src1);
637 tcg_gen_mov_tl(cpu_cc_src2, src2);
638 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
640 gen_cc_NZ_icc(cpu_cc_dst);
641 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
642 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
643 #ifdef TARGET_SPARC64
645 gen_cc_NZ_xcc(cpu_cc_dst);
646 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
647 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
649 tcg_gen_mov_tl(dst, cpu_cc_dst);
652 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
654 tcg_gen_mov_tl(cpu_cc_src, src1);
655 tcg_gen_mov_tl(cpu_cc_src2, src2);
656 gen_mov_reg_C(cpu_tmp0, cpu_psr);
657 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
659 gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
660 #ifdef TARGET_SPARC64
662 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
664 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
665 gen_cc_NZ_icc(cpu_cc_dst);
666 gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
667 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
668 #ifdef TARGET_SPARC64
669 gen_cc_NZ_xcc(cpu_cc_dst);
670 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
671 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
673 tcg_gen_mov_tl(dst, cpu_cc_dst);
676 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
678 tcg_gen_mov_tl(cpu_cc_src, src1);
679 tcg_gen_mov_tl(cpu_cc_src2, src2);
680 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
682 gen_cc_NZ_icc(cpu_cc_dst);
683 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
684 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
685 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
686 #ifdef TARGET_SPARC64
688 gen_cc_NZ_xcc(cpu_cc_dst);
689 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
690 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
692 tcg_gen_mov_tl(dst, cpu_cc_dst);
695 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
697 tcg_gen_mov_tl(cpu_cc_src, src1);
698 tcg_gen_mov_tl(cpu_cc_src2, src2);
699 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
700 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
701 gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
703 gen_cc_NZ_icc(cpu_cc_dst);
704 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
705 #ifdef TARGET_SPARC64
707 gen_cc_NZ_xcc(cpu_cc_dst);
708 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
709 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
711 tcg_gen_mov_tl(dst, cpu_cc_dst);
714 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
719 l1 = gen_new_label();
720 r_temp = tcg_temp_new(TCG_TYPE_TL);
726 tcg_gen_mov_tl(cpu_cc_src, src1);
727 tcg_gen_ld_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
728 tcg_gen_andi_tl(r_temp, r_temp, 0x1);
729 tcg_gen_mov_tl(cpu_cc_src2, src2);
730 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
731 tcg_gen_movi_tl(cpu_cc_src2, 0);
735 // env->y = (b2 << 31) | (env->y >> 1);
736 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
737 tcg_gen_shli_tl(r_temp, r_temp, 31);
738 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
739 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 1);
740 tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
741 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
744 gen_mov_reg_N(cpu_tmp0, cpu_psr);
745 gen_mov_reg_V(r_temp, cpu_psr);
746 tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
747 tcg_temp_free(r_temp);
749 // T0 = (b1 << 31) | (T0 >> 1);
751 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
752 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
753 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
755 /* do addition and update flags */
756 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
759 gen_cc_NZ_icc(cpu_cc_dst);
760 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
761 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
762 tcg_gen_mov_tl(dst, cpu_cc_dst);
765 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
767 TCGv r_temp, r_temp2;
769 r_temp = tcg_temp_new(TCG_TYPE_I64);
770 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
772 tcg_gen_extu_tl_i64(r_temp, src2);
773 tcg_gen_extu_tl_i64(r_temp2, src1);
774 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
776 tcg_gen_shri_i64(r_temp, r_temp2, 32);
777 tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
778 tcg_temp_free(r_temp);
779 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
780 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
781 #ifdef TARGET_SPARC64
782 tcg_gen_mov_i64(dst, r_temp2);
784 tcg_gen_trunc_i64_tl(dst, r_temp2);
786 tcg_temp_free(r_temp2);
789 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
791 TCGv r_temp, r_temp2;
793 r_temp = tcg_temp_new(TCG_TYPE_I64);
794 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
796 tcg_gen_ext_tl_i64(r_temp, src2);
797 tcg_gen_ext_tl_i64(r_temp2, src1);
798 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
800 tcg_gen_shri_i64(r_temp, r_temp2, 32);
801 tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
802 tcg_temp_free(r_temp);
803 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
804 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
805 #ifdef TARGET_SPARC64
806 tcg_gen_mov_i64(dst, r_temp2);
808 tcg_gen_trunc_i64_tl(dst, r_temp2);
810 tcg_temp_free(r_temp2);
813 #ifdef TARGET_SPARC64
814 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
819 l1 = gen_new_label();
820 tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
821 r_const = tcg_const_i32(TT_DIV_ZERO);
822 tcg_gen_helper_0_1(raise_exception, r_const);
823 tcg_temp_free(r_const);
827 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
831 l1 = gen_new_label();
832 l2 = gen_new_label();
833 tcg_gen_mov_tl(cpu_cc_src, src1);
834 tcg_gen_mov_tl(cpu_cc_src2, src2);
835 gen_trap_ifdivzero_tl(cpu_cc_src2);
836 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
837 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
838 tcg_gen_movi_i64(dst, INT64_MIN);
841 tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
846 static inline void gen_op_div_cc(TCGv dst)
850 tcg_gen_mov_tl(cpu_cc_dst, dst);
852 gen_cc_NZ_icc(cpu_cc_dst);
853 l1 = gen_new_label();
854 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
855 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
859 static inline void gen_op_logic_cc(TCGv dst)
861 tcg_gen_mov_tl(cpu_cc_dst, dst);
864 gen_cc_NZ_icc(cpu_cc_dst);
865 #ifdef TARGET_SPARC64
867 gen_cc_NZ_xcc(cpu_cc_dst);
872 static inline void gen_op_eval_ba(TCGv dst)
874 tcg_gen_movi_tl(dst, 1);
878 static inline void gen_op_eval_be(TCGv dst, TCGv src)
880 gen_mov_reg_Z(dst, src);
884 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
886 gen_mov_reg_N(cpu_tmp0, src);
887 gen_mov_reg_V(dst, src);
888 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
889 gen_mov_reg_Z(cpu_tmp0, src);
890 tcg_gen_or_tl(dst, dst, cpu_tmp0);
894 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
896 gen_mov_reg_V(cpu_tmp0, src);
897 gen_mov_reg_N(dst, src);
898 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
902 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
904 gen_mov_reg_Z(cpu_tmp0, src);
905 gen_mov_reg_C(dst, src);
906 tcg_gen_or_tl(dst, dst, cpu_tmp0);
910 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
912 gen_mov_reg_C(dst, src);
916 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
918 gen_mov_reg_V(dst, src);
922 static inline void gen_op_eval_bn(TCGv dst)
924 tcg_gen_movi_tl(dst, 0);
928 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
930 gen_mov_reg_N(dst, src);
934 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
936 gen_mov_reg_Z(dst, src);
937 tcg_gen_xori_tl(dst, dst, 0x1);
941 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
943 gen_mov_reg_N(cpu_tmp0, src);
944 gen_mov_reg_V(dst, src);
945 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
946 gen_mov_reg_Z(cpu_tmp0, src);
947 tcg_gen_or_tl(dst, dst, cpu_tmp0);
948 tcg_gen_xori_tl(dst, dst, 0x1);
952 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
954 gen_mov_reg_V(cpu_tmp0, src);
955 gen_mov_reg_N(dst, src);
956 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
957 tcg_gen_xori_tl(dst, dst, 0x1);
961 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
963 gen_mov_reg_Z(cpu_tmp0, src);
964 gen_mov_reg_C(dst, src);
965 tcg_gen_or_tl(dst, dst, cpu_tmp0);
966 tcg_gen_xori_tl(dst, dst, 0x1);
970 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
972 gen_mov_reg_C(dst, src);
973 tcg_gen_xori_tl(dst, dst, 0x1);
977 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
979 gen_mov_reg_N(dst, src);
980 tcg_gen_xori_tl(dst, dst, 0x1);
984 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
986 gen_mov_reg_V(dst, src);
987 tcg_gen_xori_tl(dst, dst, 0x1);
991 FPSR bit field FCC1 | FCC0:
997 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
998 unsigned int fcc_offset)
1000 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
1001 tcg_gen_andi_tl(reg, reg, 0x1);
1004 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1005 unsigned int fcc_offset)
1007 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
1008 tcg_gen_andi_tl(reg, reg, 0x1);
1012 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1013 unsigned int fcc_offset)
1015 gen_mov_reg_FCC0(dst, src, fcc_offset);
1016 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1017 tcg_gen_or_tl(dst, dst, cpu_tmp0);
1020 // 1 or 2: FCC0 ^ FCC1
1021 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1022 unsigned int fcc_offset)
1024 gen_mov_reg_FCC0(dst, src, fcc_offset);
1025 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1026 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1030 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1031 unsigned int fcc_offset)
1033 gen_mov_reg_FCC0(dst, src, fcc_offset);
1037 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1038 unsigned int fcc_offset)
1040 gen_mov_reg_FCC0(dst, src, fcc_offset);
1041 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1042 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1043 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1047 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1048 unsigned int fcc_offset)
1050 gen_mov_reg_FCC1(dst, src, fcc_offset);
1054 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1055 unsigned int fcc_offset)
1057 gen_mov_reg_FCC0(dst, src, fcc_offset);
1058 tcg_gen_xori_tl(dst, dst, 0x1);
1059 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1060 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1064 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1065 unsigned int fcc_offset)
1067 gen_mov_reg_FCC0(dst, src, fcc_offset);
1068 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1069 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1072 // 0: !(FCC0 | FCC1)
1073 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1074 unsigned int fcc_offset)
1076 gen_mov_reg_FCC0(dst, src, fcc_offset);
1077 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1078 tcg_gen_or_tl(dst, dst, cpu_tmp0);
1079 tcg_gen_xori_tl(dst, dst, 0x1);
1082 // 0 or 3: !(FCC0 ^ FCC1)
1083 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1084 unsigned int fcc_offset)
1086 gen_mov_reg_FCC0(dst, src, fcc_offset);
1087 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1088 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1089 tcg_gen_xori_tl(dst, dst, 0x1);
1093 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1094 unsigned int fcc_offset)
1096 gen_mov_reg_FCC0(dst, src, fcc_offset);
1097 tcg_gen_xori_tl(dst, dst, 0x1);
1100 // !1: !(FCC0 & !FCC1)
1101 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1102 unsigned int fcc_offset)
1104 gen_mov_reg_FCC0(dst, src, fcc_offset);
1105 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1106 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1107 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1108 tcg_gen_xori_tl(dst, dst, 0x1);
1112 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1113 unsigned int fcc_offset)
1115 gen_mov_reg_FCC1(dst, src, fcc_offset);
1116 tcg_gen_xori_tl(dst, dst, 0x1);
1119 // !2: !(!FCC0 & FCC1)
1120 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1121 unsigned int fcc_offset)
1123 gen_mov_reg_FCC0(dst, src, fcc_offset);
1124 tcg_gen_xori_tl(dst, dst, 0x1);
1125 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1126 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1127 tcg_gen_xori_tl(dst, dst, 0x1);
1130 // !3: !(FCC0 & FCC1)
1131 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1132 unsigned int fcc_offset)
1134 gen_mov_reg_FCC0(dst, src, fcc_offset);
1135 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1136 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1137 tcg_gen_xori_tl(dst, dst, 0x1);
1140 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1141 target_ulong pc2, TCGv r_cond)
1145 l1 = gen_new_label();
1147 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1149 gen_goto_tb(dc, 0, pc1, pc1 + 4);
1152 gen_goto_tb(dc, 1, pc2, pc2 + 4);
1155 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1156 target_ulong pc2, TCGv r_cond)
1160 l1 = gen_new_label();
1162 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1164 gen_goto_tb(dc, 0, pc2, pc1);
1167 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1170 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1175 l1 = gen_new_label();
1176 l2 = gen_new_label();
1178 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1180 tcg_gen_movi_tl(cpu_npc, npc1);
1184 tcg_gen_movi_tl(cpu_npc, npc2);
1188 /* call this function before using the condition register as it may
1189 have been set for a jump */
1190 static inline void flush_cond(DisasContext *dc, TCGv cond)
1192 if (dc->npc == JUMP_PC) {
1193 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1194 dc->npc = DYNAMIC_PC;
1198 static inline void save_npc(DisasContext *dc, TCGv cond)
1200 if (dc->npc == JUMP_PC) {
1201 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1202 dc->npc = DYNAMIC_PC;
1203 } else if (dc->npc != DYNAMIC_PC) {
1204 tcg_gen_movi_tl(cpu_npc, dc->npc);
1208 static inline void save_state(DisasContext *dc, TCGv cond)
1210 tcg_gen_movi_tl(cpu_pc, dc->pc);
1214 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1216 if (dc->npc == JUMP_PC) {
1217 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1218 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1219 dc->pc = DYNAMIC_PC;
1220 } else if (dc->npc == DYNAMIC_PC) {
1221 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1222 dc->pc = DYNAMIC_PC;
1228 static inline void gen_op_next_insn(void)
1230 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1231 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1234 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1238 #ifdef TARGET_SPARC64
1248 gen_op_eval_bn(r_dst);
1251 gen_op_eval_be(r_dst, r_src);
1254 gen_op_eval_ble(r_dst, r_src);
1257 gen_op_eval_bl(r_dst, r_src);
1260 gen_op_eval_bleu(r_dst, r_src);
1263 gen_op_eval_bcs(r_dst, r_src);
1266 gen_op_eval_bneg(r_dst, r_src);
1269 gen_op_eval_bvs(r_dst, r_src);
1272 gen_op_eval_ba(r_dst);
1275 gen_op_eval_bne(r_dst, r_src);
1278 gen_op_eval_bg(r_dst, r_src);
1281 gen_op_eval_bge(r_dst, r_src);
1284 gen_op_eval_bgu(r_dst, r_src);
1287 gen_op_eval_bcc(r_dst, r_src);
1290 gen_op_eval_bpos(r_dst, r_src);
1293 gen_op_eval_bvc(r_dst, r_src);
1298 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1300 unsigned int offset;
1320 gen_op_eval_bn(r_dst);
1323 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1326 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1329 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1332 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1335 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1338 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1341 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1344 gen_op_eval_ba(r_dst);
1347 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1350 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1353 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1356 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1359 gen_op_eval_fble(r_dst, cpu_fsr, offset);
1362 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1365 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1370 #ifdef TARGET_SPARC64
1372 static const int gen_tcg_cond_reg[8] = {
1383 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1387 l1 = gen_new_label();
1388 tcg_gen_movi_tl(r_dst, 0);
1389 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1390 tcg_gen_movi_tl(r_dst, 1);
1395 /* XXX: potentially incorrect if dynamic npc */
1396 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1399 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1400 target_ulong target = dc->pc + offset;
1403 /* unconditional not taken */
1405 dc->pc = dc->npc + 4;
1406 dc->npc = dc->pc + 4;
1409 dc->npc = dc->pc + 4;
1411 } else if (cond == 0x8) {
1412 /* unconditional taken */
1415 dc->npc = dc->pc + 4;
1421 flush_cond(dc, r_cond);
1422 gen_cond(r_cond, cc, cond);
1424 gen_branch_a(dc, target, dc->npc, r_cond);
1428 dc->jump_pc[0] = target;
1429 dc->jump_pc[1] = dc->npc + 4;
1435 /* XXX: potentially incorrect if dynamic npc */
1436 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1439 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1440 target_ulong target = dc->pc + offset;
1443 /* unconditional not taken */
1445 dc->pc = dc->npc + 4;
1446 dc->npc = dc->pc + 4;
1449 dc->npc = dc->pc + 4;
1451 } else if (cond == 0x8) {
1452 /* unconditional taken */
1455 dc->npc = dc->pc + 4;
1461 flush_cond(dc, r_cond);
1462 gen_fcond(r_cond, cc, cond);
1464 gen_branch_a(dc, target, dc->npc, r_cond);
1468 dc->jump_pc[0] = target;
1469 dc->jump_pc[1] = dc->npc + 4;
1475 #ifdef TARGET_SPARC64
1476 /* XXX: potentially incorrect if dynamic npc */
1477 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1478 TCGv r_cond, TCGv r_reg)
1480 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1481 target_ulong target = dc->pc + offset;
1483 flush_cond(dc, r_cond);
1484 gen_cond_reg(r_cond, cond, r_reg);
1486 gen_branch_a(dc, target, dc->npc, r_cond);
1490 dc->jump_pc[0] = target;
1491 dc->jump_pc[1] = dc->npc + 4;
1496 static GenOpFunc * const gen_fcmps[4] = {
1503 static GenOpFunc * const gen_fcmpd[4] = {
1510 static GenOpFunc * const gen_fcmpq[4] = {
1517 static GenOpFunc * const gen_fcmpes[4] = {
1524 static GenOpFunc * const gen_fcmped[4] = {
1531 static GenOpFunc * const gen_fcmpeq[4] = {
1538 static inline void gen_op_fcmps(int fccno)
1540 tcg_gen_helper_0_0(gen_fcmps[fccno]);
1543 static inline void gen_op_fcmpd(int fccno)
1545 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1548 static inline void gen_op_fcmpq(int fccno)
1550 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1553 static inline void gen_op_fcmpes(int fccno)
1555 tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1558 static inline void gen_op_fcmped(int fccno)
1560 tcg_gen_helper_0_0(gen_fcmped[fccno]);
1563 static inline void gen_op_fcmpeq(int fccno)
1565 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1570 static inline void gen_op_fcmps(int fccno)
1572 tcg_gen_helper_0_0(helper_fcmps);
1575 static inline void gen_op_fcmpd(int fccno)
1577 tcg_gen_helper_0_0(helper_fcmpd);
1580 static inline void gen_op_fcmpq(int fccno)
1582 tcg_gen_helper_0_0(helper_fcmpq);
1585 static inline void gen_op_fcmpes(int fccno)
1587 tcg_gen_helper_0_0(helper_fcmpes);
1590 static inline void gen_op_fcmped(int fccno)
1592 tcg_gen_helper_0_0(helper_fcmped);
1595 static inline void gen_op_fcmpeq(int fccno)
1597 tcg_gen_helper_0_0(helper_fcmpeq);
1601 static inline void gen_op_fpexception_im(int fsr_flags)
1605 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1606 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1607 r_const = tcg_const_i32(TT_FP_EXCP);
1608 tcg_gen_helper_0_1(raise_exception, r_const);
1609 tcg_temp_free(r_const);
1612 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1614 #if !defined(CONFIG_USER_ONLY)
1615 if (!dc->fpu_enabled) {
1618 save_state(dc, r_cond);
1619 r_const = tcg_const_i32(TT_NFPU_INSN);
1620 tcg_gen_helper_0_1(raise_exception, r_const);
1621 tcg_temp_free(r_const);
1629 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1631 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1634 static inline void gen_clear_float_exceptions(void)
1636 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1640 #ifdef TARGET_SPARC64
1641 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1647 r_asi = tcg_temp_new(TCG_TYPE_I32);
1648 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1650 asi = GET_FIELD(insn, 19, 26);
1651 r_asi = tcg_const_i32(asi);
1656 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1659 TCGv r_asi, r_size, r_sign;
1661 r_asi = gen_get_asi(insn, addr);
1662 r_size = tcg_const_i32(size);
1663 r_sign = tcg_const_i32(sign);
1664 tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1665 tcg_temp_free(r_sign);
1666 tcg_temp_free(r_size);
1667 tcg_temp_free(r_asi);
1670 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1674 r_asi = gen_get_asi(insn, addr);
1675 r_size = tcg_const_i32(size);
1676 tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1677 tcg_temp_free(r_size);
1678 tcg_temp_free(r_asi);
1681 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1683 TCGv r_asi, r_size, r_rd;
1685 r_asi = gen_get_asi(insn, addr);
1686 r_size = tcg_const_i32(size);
1687 r_rd = tcg_const_i32(rd);
1688 tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1689 tcg_temp_free(r_rd);
1690 tcg_temp_free(r_size);
1691 tcg_temp_free(r_asi);
1694 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1696 TCGv r_asi, r_size, r_rd;
1698 r_asi = gen_get_asi(insn, addr);
1699 r_size = tcg_const_i32(size);
1700 r_rd = tcg_const_i32(rd);
1701 tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1702 tcg_temp_free(r_rd);
1703 tcg_temp_free(r_size);
1704 tcg_temp_free(r_asi);
1707 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1709 TCGv r_asi, r_size, r_sign;
1711 r_asi = gen_get_asi(insn, addr);
1712 r_size = tcg_const_i32(4);
1713 r_sign = tcg_const_i32(0);
1714 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1715 tcg_temp_free(r_sign);
1716 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1717 tcg_temp_free(r_size);
1718 tcg_temp_free(r_asi);
1719 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1722 static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1726 r_asi = gen_get_asi(insn, addr);
1727 r_rd = tcg_const_i32(rd);
1728 tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd);
1729 tcg_temp_free(r_rd);
1730 tcg_temp_free(r_asi);
1733 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1735 TCGv r_temp, r_asi, r_size;
1737 r_temp = tcg_temp_new(TCG_TYPE_TL);
1738 gen_movl_reg_TN(rd + 1, r_temp);
1739 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1741 tcg_temp_free(r_temp);
1742 r_asi = gen_get_asi(insn, addr);
1743 r_size = tcg_const_i32(8);
1744 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1745 tcg_temp_free(r_size);
1746 tcg_temp_free(r_asi);
1749 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1754 r_val1 = tcg_temp_new(TCG_TYPE_TL);
1755 gen_movl_reg_TN(rd, r_val1);
1756 r_asi = gen_get_asi(insn, addr);
1757 tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1758 tcg_temp_free(r_asi);
1759 tcg_temp_free(r_val1);
1762 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1767 gen_movl_reg_TN(rd, cpu_tmp64);
1768 r_asi = gen_get_asi(insn, addr);
1769 tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1770 tcg_temp_free(r_asi);
1773 #elif !defined(CONFIG_USER_ONLY)
1775 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1778 TCGv r_asi, r_size, r_sign;
1780 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1781 r_size = tcg_const_i32(size);
1782 r_sign = tcg_const_i32(sign);
1783 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1784 tcg_temp_free(r_sign);
1785 tcg_temp_free(r_size);
1786 tcg_temp_free(r_asi);
1787 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1790 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1794 tcg_gen_extu_tl_i64(cpu_tmp64, src);
1795 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1796 r_size = tcg_const_i32(size);
1797 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1798 tcg_temp_free(r_size);
1799 tcg_temp_free(r_asi);
1802 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1804 TCGv r_asi, r_size, r_sign;
1806 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1807 r_size = tcg_const_i32(4);
1808 r_sign = tcg_const_i32(0);
1809 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1810 tcg_temp_free(r_sign);
1811 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1812 tcg_temp_free(r_size);
1813 tcg_temp_free(r_asi);
1814 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1817 static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1819 TCGv r_asi, r_size, r_sign;
1821 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1822 r_size = tcg_const_i32(8);
1823 r_sign = tcg_const_i32(0);
1824 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1825 tcg_temp_free(r_sign);
1826 tcg_temp_free(r_size);
1827 tcg_temp_free(r_asi);
1828 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1829 gen_movl_TN_reg(rd + 1, cpu_tmp0);
1830 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1831 tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1832 gen_movl_TN_reg(rd, hi);
1835 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1837 TCGv r_temp, r_asi, r_size;
1839 r_temp = tcg_temp_new(TCG_TYPE_TL);
1840 gen_movl_reg_TN(rd + 1, r_temp);
1841 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1842 tcg_temp_free(r_temp);
1843 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1844 r_size = tcg_const_i32(8);
1845 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1846 tcg_temp_free(r_size);
1847 tcg_temp_free(r_asi);
1851 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1852 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1854 TCGv r_val, r_asi, r_size;
1856 gen_ld_asi(dst, addr, insn, 1, 0);
1858 r_val = tcg_const_i64(0xffULL);
1859 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1860 r_size = tcg_const_i32(1);
1861 tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1862 tcg_temp_free(r_size);
1863 tcg_temp_free(r_asi);
1864 tcg_temp_free(r_val);
1868 static inline TCGv get_src1(unsigned int insn, TCGv def)
1873 rs1 = GET_FIELD(insn, 13, 17);
1875 r_rs1 = tcg_const_tl(0); // XXX how to free?
1877 r_rs1 = cpu_gregs[rs1];
1879 tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1883 static inline TCGv get_src2(unsigned int insn, TCGv def)
1888 if (IS_IMM) { /* immediate */
1889 rs2 = GET_FIELDs(insn, 19, 31);
1890 r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1891 } else { /* register */
1892 rs2 = GET_FIELD(insn, 27, 31);
1894 r_rs2 = tcg_const_tl(0); // XXX how to free?
1896 r_rs2 = cpu_gregs[rs2];
1898 tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1903 #define CHECK_IU_FEATURE(dc, FEATURE) \
1904 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1906 #define CHECK_FPU_FEATURE(dc, FEATURE) \
1907 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1910 /* before an instruction, dc->pc must be static */
1911 static void disas_sparc_insn(DisasContext * dc)
1913 unsigned int insn, opc, rs1, rs2, rd;
1915 if (unlikely(loglevel & CPU_LOG_TB_OP))
1916 tcg_gen_debug_insn_start(dc->pc);
1917 insn = ldl_code(dc->pc);
1918 opc = GET_FIELD(insn, 0, 1);
1920 rd = GET_FIELD(insn, 2, 6);
1922 cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1923 cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1926 case 0: /* branches/sethi */
1928 unsigned int xop = GET_FIELD(insn, 7, 9);
1931 #ifdef TARGET_SPARC64
1932 case 0x1: /* V9 BPcc */
1936 target = GET_FIELD_SP(insn, 0, 18);
1937 target = sign_extend(target, 18);
1939 cc = GET_FIELD_SP(insn, 20, 21);
1941 do_branch(dc, target, insn, 0, cpu_cond);
1943 do_branch(dc, target, insn, 1, cpu_cond);
1948 case 0x3: /* V9 BPr */
1950 target = GET_FIELD_SP(insn, 0, 13) |
1951 (GET_FIELD_SP(insn, 20, 21) << 14);
1952 target = sign_extend(target, 16);
1954 cpu_src1 = get_src1(insn, cpu_src1);
1955 do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1958 case 0x5: /* V9 FBPcc */
1960 int cc = GET_FIELD_SP(insn, 20, 21);
1961 if (gen_trap_ifnofpu(dc, cpu_cond))
1963 target = GET_FIELD_SP(insn, 0, 18);
1964 target = sign_extend(target, 19);
1966 do_fbranch(dc, target, insn, cc, cpu_cond);
1970 case 0x7: /* CBN+x */
1975 case 0x2: /* BN+x */
1977 target = GET_FIELD(insn, 10, 31);
1978 target = sign_extend(target, 22);
1980 do_branch(dc, target, insn, 0, cpu_cond);
1983 case 0x6: /* FBN+x */
1985 if (gen_trap_ifnofpu(dc, cpu_cond))
1987 target = GET_FIELD(insn, 10, 31);
1988 target = sign_extend(target, 22);
1990 do_fbranch(dc, target, insn, 0, cpu_cond);
1993 case 0x4: /* SETHI */
1995 uint32_t value = GET_FIELD(insn, 10, 31);
1998 r_const = tcg_const_tl(value << 10);
1999 gen_movl_TN_reg(rd, r_const);
2000 tcg_temp_free(r_const);
2003 case 0x0: /* UNIMPL */
2012 target_long target = GET_FIELDs(insn, 2, 31) << 2;
2015 r_const = tcg_const_tl(dc->pc);
2016 gen_movl_TN_reg(15, r_const);
2017 tcg_temp_free(r_const);
2019 gen_mov_pc_npc(dc, cpu_cond);
2023 case 2: /* FPU & Logical Operations */
2025 unsigned int xop = GET_FIELD(insn, 7, 12);
2026 if (xop == 0x3a) { /* generate trap */
2029 cpu_src1 = get_src1(insn, cpu_src1);
2031 rs2 = GET_FIELD(insn, 25, 31);
2032 tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2034 rs2 = GET_FIELD(insn, 27, 31);
2036 gen_movl_reg_TN(rs2, cpu_src2);
2037 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2039 tcg_gen_mov_tl(cpu_dst, cpu_src1);
2041 cond = GET_FIELD(insn, 3, 6);
2043 save_state(dc, cpu_cond);
2044 tcg_gen_helper_0_1(helper_trap, cpu_dst);
2045 } else if (cond != 0) {
2046 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2047 #ifdef TARGET_SPARC64
2049 int cc = GET_FIELD_SP(insn, 11, 12);
2051 save_state(dc, cpu_cond);
2053 gen_cond(r_cond, 0, cond);
2055 gen_cond(r_cond, 1, cond);
2059 save_state(dc, cpu_cond);
2060 gen_cond(r_cond, 0, cond);
2062 tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2063 tcg_temp_free(r_cond);
2069 } else if (xop == 0x28) {
2070 rs1 = GET_FIELD(insn, 13, 17);
2073 #ifndef TARGET_SPARC64
2074 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2075 manual, rdy on the microSPARC
2077 case 0x0f: /* stbar in the SPARCv8 manual,
2078 rdy on the microSPARC II */
2079 case 0x10 ... 0x1f: /* implementation-dependent in the
2080 SPARCv8 manual, rdy on the
2083 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2084 offsetof(CPUSPARCState, y));
2085 gen_movl_TN_reg(rd, cpu_tmp0);
2087 #ifdef TARGET_SPARC64
2088 case 0x2: /* V9 rdccr */
2089 tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2090 gen_movl_TN_reg(rd, cpu_dst);
2092 case 0x3: /* V9 rdasi */
2093 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2094 offsetof(CPUSPARCState, asi));
2095 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2096 gen_movl_TN_reg(rd, cpu_dst);
2098 case 0x4: /* V9 rdtick */
2102 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2103 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2104 offsetof(CPUState, tick));
2105 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2107 tcg_temp_free(r_tickptr);
2108 gen_movl_TN_reg(rd, cpu_dst);
2111 case 0x5: /* V9 rdpc */
2115 r_const = tcg_const_tl(dc->pc);
2116 gen_movl_TN_reg(rd, r_const);
2117 tcg_temp_free(r_const);
2120 case 0x6: /* V9 rdfprs */
2121 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2122 offsetof(CPUSPARCState, fprs));
2123 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2124 gen_movl_TN_reg(rd, cpu_dst);
2126 case 0xf: /* V9 membar */
2127 break; /* no effect */
2128 case 0x13: /* Graphics Status */
2129 if (gen_trap_ifnofpu(dc, cpu_cond))
2131 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2132 offsetof(CPUSPARCState, gsr));
2133 gen_movl_TN_reg(rd, cpu_tmp0);
2135 case 0x17: /* Tick compare */
2136 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2137 offsetof(CPUSPARCState, tick_cmpr));
2138 gen_movl_TN_reg(rd, cpu_tmp0);
2140 case 0x18: /* System tick */
2144 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2145 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2146 offsetof(CPUState, stick));
2147 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2149 tcg_temp_free(r_tickptr);
2150 gen_movl_TN_reg(rd, cpu_dst);
2153 case 0x19: /* System tick compare */
2154 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2155 offsetof(CPUSPARCState, stick_cmpr));
2156 gen_movl_TN_reg(rd, cpu_tmp0);
2158 case 0x10: /* Performance Control */
2159 case 0x11: /* Performance Instrumentation Counter */
2160 case 0x12: /* Dispatch Control */
2161 case 0x14: /* Softint set, WO */
2162 case 0x15: /* Softint clear, WO */
2163 case 0x16: /* Softint write */
2168 #if !defined(CONFIG_USER_ONLY)
2169 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2170 #ifndef TARGET_SPARC64
2171 if (!supervisor(dc))
2173 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2175 CHECK_IU_FEATURE(dc, HYPV);
2176 if (!hypervisor(dc))
2178 rs1 = GET_FIELD(insn, 13, 17);
2181 // gen_op_rdhpstate();
2184 // gen_op_rdhtstate();
2187 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2188 offsetof(CPUSPARCState, hintp));
2189 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2192 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2193 offsetof(CPUSPARCState, htba));
2194 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2197 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2198 offsetof(CPUSPARCState, hver));
2199 tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2201 case 31: // hstick_cmpr
2202 tcg_gen_ld_tl(cpu_dst, cpu_env,
2203 offsetof(CPUSPARCState, hstick_cmpr));
2209 gen_movl_TN_reg(rd, cpu_dst);
2211 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2212 if (!supervisor(dc))
2214 #ifdef TARGET_SPARC64
2215 rs1 = GET_FIELD(insn, 13, 17);
2221 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2222 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2223 offsetof(CPUState, tsptr));
2224 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2225 offsetof(trap_state, tpc));
2226 tcg_temp_free(r_tsptr);
2233 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2234 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2235 offsetof(CPUState, tsptr));
2236 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2237 offsetof(trap_state, tnpc));
2238 tcg_temp_free(r_tsptr);
2245 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2246 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2247 offsetof(CPUState, tsptr));
2248 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2249 offsetof(trap_state, tstate));
2250 tcg_temp_free(r_tsptr);
2257 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2258 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2259 offsetof(CPUState, tsptr));
2260 tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2261 offsetof(trap_state, tt));
2262 tcg_temp_free(r_tsptr);
2269 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2270 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2271 offsetof(CPUState, tick));
2272 tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2274 gen_movl_TN_reg(rd, cpu_tmp0);
2275 tcg_temp_free(r_tickptr);
2279 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2280 offsetof(CPUSPARCState, tbr));
2283 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2284 offsetof(CPUSPARCState, pstate));
2285 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2288 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2289 offsetof(CPUSPARCState, tl));
2290 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2293 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2294 offsetof(CPUSPARCState, psrpil));
2295 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2298 tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2301 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2302 offsetof(CPUSPARCState, cansave));
2303 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2305 case 11: // canrestore
2306 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2307 offsetof(CPUSPARCState, canrestore));
2308 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2310 case 12: // cleanwin
2311 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2312 offsetof(CPUSPARCState, cleanwin));
2313 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2315 case 13: // otherwin
2316 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2317 offsetof(CPUSPARCState, otherwin));
2318 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2321 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2322 offsetof(CPUSPARCState, wstate));
2323 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2325 case 16: // UA2005 gl
2326 CHECK_IU_FEATURE(dc, GL);
2327 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2328 offsetof(CPUSPARCState, gl));
2329 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2331 case 26: // UA2005 strand status
2332 CHECK_IU_FEATURE(dc, HYPV);
2333 if (!hypervisor(dc))
2335 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2336 offsetof(CPUSPARCState, ssr));
2337 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2340 tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2341 offsetof(CPUSPARCState, version));
2348 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2349 offsetof(CPUSPARCState, wim));
2350 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2352 gen_movl_TN_reg(rd, cpu_tmp0);
2354 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2355 #ifdef TARGET_SPARC64
2356 save_state(dc, cpu_cond);
2357 tcg_gen_helper_0_0(helper_flushw);
2359 if (!supervisor(dc))
2361 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2362 gen_movl_TN_reg(rd, cpu_tmp0);
2366 } else if (xop == 0x34) { /* FPU Operations */
2367 if (gen_trap_ifnofpu(dc, cpu_cond))
2369 gen_op_clear_ieee_excp_and_FTT();
2370 rs1 = GET_FIELD(insn, 13, 17);
2371 rs2 = GET_FIELD(insn, 27, 31);
2372 xop = GET_FIELD(insn, 18, 26);
2374 case 0x1: /* fmovs */
2375 gen_op_load_fpr_FT0(rs2);
2376 gen_op_store_FT0_fpr(rd);
2378 case 0x5: /* fnegs */
2379 gen_op_load_fpr_FT1(rs2);
2380 tcg_gen_helper_0_0(helper_fnegs);
2381 gen_op_store_FT0_fpr(rd);
2383 case 0x9: /* fabss */
2384 gen_op_load_fpr_FT1(rs2);
2385 tcg_gen_helper_0_0(helper_fabss);
2386 gen_op_store_FT0_fpr(rd);
2388 case 0x29: /* fsqrts */
2389 CHECK_FPU_FEATURE(dc, FSQRT);
2390 gen_op_load_fpr_FT1(rs2);
2391 gen_clear_float_exceptions();
2392 tcg_gen_helper_0_0(helper_fsqrts);
2393 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2394 gen_op_store_FT0_fpr(rd);
2396 case 0x2a: /* fsqrtd */
2397 CHECK_FPU_FEATURE(dc, FSQRT);
2398 gen_op_load_fpr_DT1(DFPREG(rs2));
2399 gen_clear_float_exceptions();
2400 tcg_gen_helper_0_0(helper_fsqrtd);
2401 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2402 gen_op_store_DT0_fpr(DFPREG(rd));
2404 case 0x2b: /* fsqrtq */
2405 CHECK_FPU_FEATURE(dc, FLOAT128);
2406 gen_op_load_fpr_QT1(QFPREG(rs2));
2407 gen_clear_float_exceptions();
2408 tcg_gen_helper_0_0(helper_fsqrtq);
2409 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2410 gen_op_store_QT0_fpr(QFPREG(rd));
2413 gen_op_load_fpr_FT0(rs1);
2414 gen_op_load_fpr_FT1(rs2);
2415 gen_clear_float_exceptions();
2416 tcg_gen_helper_0_0(helper_fadds);
2417 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2418 gen_op_store_FT0_fpr(rd);
2421 gen_op_load_fpr_DT0(DFPREG(rs1));
2422 gen_op_load_fpr_DT1(DFPREG(rs2));
2423 gen_clear_float_exceptions();
2424 tcg_gen_helper_0_0(helper_faddd);
2425 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2426 gen_op_store_DT0_fpr(DFPREG(rd));
2428 case 0x43: /* faddq */
2429 CHECK_FPU_FEATURE(dc, FLOAT128);
2430 gen_op_load_fpr_QT0(QFPREG(rs1));
2431 gen_op_load_fpr_QT1(QFPREG(rs2));
2432 gen_clear_float_exceptions();
2433 tcg_gen_helper_0_0(helper_faddq);
2434 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2435 gen_op_store_QT0_fpr(QFPREG(rd));
2438 gen_op_load_fpr_FT0(rs1);
2439 gen_op_load_fpr_FT1(rs2);
2440 gen_clear_float_exceptions();
2441 tcg_gen_helper_0_0(helper_fsubs);
2442 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2443 gen_op_store_FT0_fpr(rd);
2446 gen_op_load_fpr_DT0(DFPREG(rs1));
2447 gen_op_load_fpr_DT1(DFPREG(rs2));
2448 gen_clear_float_exceptions();
2449 tcg_gen_helper_0_0(helper_fsubd);
2450 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2451 gen_op_store_DT0_fpr(DFPREG(rd));
2453 case 0x47: /* fsubq */
2454 CHECK_FPU_FEATURE(dc, FLOAT128);
2455 gen_op_load_fpr_QT0(QFPREG(rs1));
2456 gen_op_load_fpr_QT1(QFPREG(rs2));
2457 gen_clear_float_exceptions();
2458 tcg_gen_helper_0_0(helper_fsubq);
2459 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2460 gen_op_store_QT0_fpr(QFPREG(rd));
2462 case 0x49: /* fmuls */
2463 CHECK_FPU_FEATURE(dc, FMUL);
2464 gen_op_load_fpr_FT0(rs1);
2465 gen_op_load_fpr_FT1(rs2);
2466 gen_clear_float_exceptions();
2467 tcg_gen_helper_0_0(helper_fmuls);
2468 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2469 gen_op_store_FT0_fpr(rd);
2471 case 0x4a: /* fmuld */
2472 CHECK_FPU_FEATURE(dc, FMUL);
2473 gen_op_load_fpr_DT0(DFPREG(rs1));
2474 gen_op_load_fpr_DT1(DFPREG(rs2));
2475 gen_clear_float_exceptions();
2476 tcg_gen_helper_0_0(helper_fmuld);
2477 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2478 gen_op_store_DT0_fpr(DFPREG(rd));
2480 case 0x4b: /* fmulq */
2481 CHECK_FPU_FEATURE(dc, FLOAT128);
2482 CHECK_FPU_FEATURE(dc, FMUL);
2483 gen_op_load_fpr_QT0(QFPREG(rs1));
2484 gen_op_load_fpr_QT1(QFPREG(rs2));
2485 gen_clear_float_exceptions();
2486 tcg_gen_helper_0_0(helper_fmulq);
2487 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2488 gen_op_store_QT0_fpr(QFPREG(rd));
2491 gen_op_load_fpr_FT0(rs1);
2492 gen_op_load_fpr_FT1(rs2);
2493 gen_clear_float_exceptions();
2494 tcg_gen_helper_0_0(helper_fdivs);
2495 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2496 gen_op_store_FT0_fpr(rd);
2499 gen_op_load_fpr_DT0(DFPREG(rs1));
2500 gen_op_load_fpr_DT1(DFPREG(rs2));
2501 gen_clear_float_exceptions();
2502 tcg_gen_helper_0_0(helper_fdivd);
2503 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2504 gen_op_store_DT0_fpr(DFPREG(rd));
2506 case 0x4f: /* fdivq */
2507 CHECK_FPU_FEATURE(dc, FLOAT128);
2508 gen_op_load_fpr_QT0(QFPREG(rs1));
2509 gen_op_load_fpr_QT1(QFPREG(rs2));
2510 gen_clear_float_exceptions();
2511 tcg_gen_helper_0_0(helper_fdivq);
2512 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2513 gen_op_store_QT0_fpr(QFPREG(rd));
2516 CHECK_FPU_FEATURE(dc, FSMULD);
2517 gen_op_load_fpr_FT0(rs1);
2518 gen_op_load_fpr_FT1(rs2);
2519 gen_clear_float_exceptions();
2520 tcg_gen_helper_0_0(helper_fsmuld);
2521 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2522 gen_op_store_DT0_fpr(DFPREG(rd));
2524 case 0x6e: /* fdmulq */
2525 CHECK_FPU_FEATURE(dc, FLOAT128);
2526 gen_op_load_fpr_DT0(DFPREG(rs1));
2527 gen_op_load_fpr_DT1(DFPREG(rs2));
2528 gen_clear_float_exceptions();
2529 tcg_gen_helper_0_0(helper_fdmulq);
2530 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2531 gen_op_store_QT0_fpr(QFPREG(rd));
2534 gen_op_load_fpr_FT1(rs2);
2535 gen_clear_float_exceptions();
2536 tcg_gen_helper_0_0(helper_fitos);
2537 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2538 gen_op_store_FT0_fpr(rd);
2541 gen_op_load_fpr_DT1(DFPREG(rs2));
2542 gen_clear_float_exceptions();
2543 tcg_gen_helper_0_0(helper_fdtos);
2544 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2545 gen_op_store_FT0_fpr(rd);
2547 case 0xc7: /* fqtos */
2548 CHECK_FPU_FEATURE(dc, FLOAT128);
2549 gen_op_load_fpr_QT1(QFPREG(rs2));
2550 gen_clear_float_exceptions();
2551 tcg_gen_helper_0_0(helper_fqtos);
2552 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2553 gen_op_store_FT0_fpr(rd);
2556 gen_op_load_fpr_FT1(rs2);
2557 tcg_gen_helper_0_0(helper_fitod);
2558 gen_op_store_DT0_fpr(DFPREG(rd));
2561 gen_op_load_fpr_FT1(rs2);
2562 tcg_gen_helper_0_0(helper_fstod);
2563 gen_op_store_DT0_fpr(DFPREG(rd));
2565 case 0xcb: /* fqtod */
2566 CHECK_FPU_FEATURE(dc, FLOAT128);
2567 gen_op_load_fpr_QT1(QFPREG(rs2));
2568 gen_clear_float_exceptions();
2569 tcg_gen_helper_0_0(helper_fqtod);
2570 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2571 gen_op_store_DT0_fpr(DFPREG(rd));
2573 case 0xcc: /* fitoq */
2574 CHECK_FPU_FEATURE(dc, FLOAT128);
2575 gen_op_load_fpr_FT1(rs2);
2576 tcg_gen_helper_0_0(helper_fitoq);
2577 gen_op_store_QT0_fpr(QFPREG(rd));
2579 case 0xcd: /* fstoq */
2580 CHECK_FPU_FEATURE(dc, FLOAT128);
2581 gen_op_load_fpr_FT1(rs2);
2582 tcg_gen_helper_0_0(helper_fstoq);
2583 gen_op_store_QT0_fpr(QFPREG(rd));
2585 case 0xce: /* fdtoq */
2586 CHECK_FPU_FEATURE(dc, FLOAT128);
2587 gen_op_load_fpr_DT1(DFPREG(rs2));
2588 tcg_gen_helper_0_0(helper_fdtoq);
2589 gen_op_store_QT0_fpr(QFPREG(rd));
2592 gen_op_load_fpr_FT1(rs2);
2593 gen_clear_float_exceptions();
2594 tcg_gen_helper_0_0(helper_fstoi);
2595 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2596 gen_op_store_FT0_fpr(rd);
2599 gen_op_load_fpr_DT1(DFPREG(rs2));
2600 gen_clear_float_exceptions();
2601 tcg_gen_helper_0_0(helper_fdtoi);
2602 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2603 gen_op_store_FT0_fpr(rd);
2605 case 0xd3: /* fqtoi */
2606 CHECK_FPU_FEATURE(dc, FLOAT128);
2607 gen_op_load_fpr_QT1(QFPREG(rs2));
2608 gen_clear_float_exceptions();
2609 tcg_gen_helper_0_0(helper_fqtoi);
2610 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2611 gen_op_store_FT0_fpr(rd);
2613 #ifdef TARGET_SPARC64
2614 case 0x2: /* V9 fmovd */
2615 gen_op_load_fpr_DT0(DFPREG(rs2));
2616 gen_op_store_DT0_fpr(DFPREG(rd));
2618 case 0x3: /* V9 fmovq */
2619 CHECK_FPU_FEATURE(dc, FLOAT128);
2620 gen_op_load_fpr_QT0(QFPREG(rs2));
2621 gen_op_store_QT0_fpr(QFPREG(rd));
2623 case 0x6: /* V9 fnegd */
2624 gen_op_load_fpr_DT1(DFPREG(rs2));
2625 tcg_gen_helper_0_0(helper_fnegd);
2626 gen_op_store_DT0_fpr(DFPREG(rd));
2628 case 0x7: /* V9 fnegq */
2629 CHECK_FPU_FEATURE(dc, FLOAT128);
2630 gen_op_load_fpr_QT1(QFPREG(rs2));
2631 tcg_gen_helper_0_0(helper_fnegq);
2632 gen_op_store_QT0_fpr(QFPREG(rd));
2634 case 0xa: /* V9 fabsd */
2635 gen_op_load_fpr_DT1(DFPREG(rs2));
2636 tcg_gen_helper_0_0(helper_fabsd);
2637 gen_op_store_DT0_fpr(DFPREG(rd));
2639 case 0xb: /* V9 fabsq */
2640 CHECK_FPU_FEATURE(dc, FLOAT128);
2641 gen_op_load_fpr_QT1(QFPREG(rs2));
2642 tcg_gen_helper_0_0(helper_fabsq);
2643 gen_op_store_QT0_fpr(QFPREG(rd));
2645 case 0x81: /* V9 fstox */
2646 gen_op_load_fpr_FT1(rs2);
2647 gen_clear_float_exceptions();
2648 tcg_gen_helper_0_0(helper_fstox);
2649 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2650 gen_op_store_DT0_fpr(DFPREG(rd));
2652 case 0x82: /* V9 fdtox */
2653 gen_op_load_fpr_DT1(DFPREG(rs2));
2654 gen_clear_float_exceptions();
2655 tcg_gen_helper_0_0(helper_fdtox);
2656 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2657 gen_op_store_DT0_fpr(DFPREG(rd));
2659 case 0x83: /* V9 fqtox */
2660 CHECK_FPU_FEATURE(dc, FLOAT128);
2661 gen_op_load_fpr_QT1(QFPREG(rs2));
2662 gen_clear_float_exceptions();
2663 tcg_gen_helper_0_0(helper_fqtox);
2664 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2665 gen_op_store_DT0_fpr(DFPREG(rd));
2667 case 0x84: /* V9 fxtos */
2668 gen_op_load_fpr_DT1(DFPREG(rs2));
2669 gen_clear_float_exceptions();
2670 tcg_gen_helper_0_0(helper_fxtos);
2671 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2672 gen_op_store_FT0_fpr(rd);
2674 case 0x88: /* V9 fxtod */
2675 gen_op_load_fpr_DT1(DFPREG(rs2));
2676 gen_clear_float_exceptions();
2677 tcg_gen_helper_0_0(helper_fxtod);
2678 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2679 gen_op_store_DT0_fpr(DFPREG(rd));
2681 case 0x8c: /* V9 fxtoq */
2682 CHECK_FPU_FEATURE(dc, FLOAT128);
2683 gen_op_load_fpr_DT1(DFPREG(rs2));
2684 gen_clear_float_exceptions();
2685 tcg_gen_helper_0_0(helper_fxtoq);
2686 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2687 gen_op_store_QT0_fpr(QFPREG(rd));
2693 } else if (xop == 0x35) { /* FPU Operations */
2694 #ifdef TARGET_SPARC64
2697 if (gen_trap_ifnofpu(dc, cpu_cond))
2699 gen_op_clear_ieee_excp_and_FTT();
2700 rs1 = GET_FIELD(insn, 13, 17);
2701 rs2 = GET_FIELD(insn, 27, 31);
2702 xop = GET_FIELD(insn, 18, 26);
2703 #ifdef TARGET_SPARC64
2704 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2707 l1 = gen_new_label();
2708 cond = GET_FIELD_SP(insn, 14, 17);
2709 cpu_src1 = get_src1(insn, cpu_src1);
2710 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2712 gen_op_load_fpr_FT0(rs2);
2713 gen_op_store_FT0_fpr(rd);
2716 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2719 l1 = gen_new_label();
2720 cond = GET_FIELD_SP(insn, 14, 17);
2721 cpu_src1 = get_src1(insn, cpu_src1);
2722 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2724 gen_op_load_fpr_DT0(DFPREG(rs2));
2725 gen_op_store_DT0_fpr(DFPREG(rd));
2728 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2731 CHECK_FPU_FEATURE(dc, FLOAT128);
2732 l1 = gen_new_label();
2733 cond = GET_FIELD_SP(insn, 14, 17);
2734 cpu_src1 = get_src1(insn, cpu_src1);
2735 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2737 gen_op_load_fpr_QT0(QFPREG(rs2));
2738 gen_op_store_QT0_fpr(QFPREG(rd));
2744 #ifdef TARGET_SPARC64
2745 #define FMOVCC(size_FDQ, fcc) \
2750 l1 = gen_new_label(); \
2751 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2752 cond = GET_FIELD_SP(insn, 14, 17); \
2753 gen_fcond(r_cond, fcc, cond); \
2754 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2756 glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2757 (glue(size_FDQ, FPREG(rs2))); \
2758 glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2759 (glue(size_FDQ, FPREG(rd))); \
2760 gen_set_label(l1); \
2761 tcg_temp_free(r_cond); \
2763 case 0x001: /* V9 fmovscc %fcc0 */
2766 case 0x002: /* V9 fmovdcc %fcc0 */
2769 case 0x003: /* V9 fmovqcc %fcc0 */
2770 CHECK_FPU_FEATURE(dc, FLOAT128);
2773 case 0x041: /* V9 fmovscc %fcc1 */
2776 case 0x042: /* V9 fmovdcc %fcc1 */
2779 case 0x043: /* V9 fmovqcc %fcc1 */
2780 CHECK_FPU_FEATURE(dc, FLOAT128);
2783 case 0x081: /* V9 fmovscc %fcc2 */
2786 case 0x082: /* V9 fmovdcc %fcc2 */
2789 case 0x083: /* V9 fmovqcc %fcc2 */
2790 CHECK_FPU_FEATURE(dc, FLOAT128);
2793 case 0x0c1: /* V9 fmovscc %fcc3 */
2796 case 0x0c2: /* V9 fmovdcc %fcc3 */
2799 case 0x0c3: /* V9 fmovqcc %fcc3 */
2800 CHECK_FPU_FEATURE(dc, FLOAT128);
2804 #define FMOVCC(size_FDQ, icc) \
2809 l1 = gen_new_label(); \
2810 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2811 cond = GET_FIELD_SP(insn, 14, 17); \
2812 gen_cond(r_cond, icc, cond); \
2813 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2815 glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2816 (glue(size_FDQ, FPREG(rs2))); \
2817 glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2818 (glue(size_FDQ, FPREG(rd))); \
2819 gen_set_label(l1); \
2820 tcg_temp_free(r_cond); \
2823 case 0x101: /* V9 fmovscc %icc */
2826 case 0x102: /* V9 fmovdcc %icc */
2828 case 0x103: /* V9 fmovqcc %icc */
2829 CHECK_FPU_FEATURE(dc, FLOAT128);
2832 case 0x181: /* V9 fmovscc %xcc */
2835 case 0x182: /* V9 fmovdcc %xcc */
2838 case 0x183: /* V9 fmovqcc %xcc */
2839 CHECK_FPU_FEATURE(dc, FLOAT128);
2844 case 0x51: /* fcmps, V9 %fcc */
2845 gen_op_load_fpr_FT0(rs1);
2846 gen_op_load_fpr_FT1(rs2);
2847 gen_op_fcmps(rd & 3);
2849 case 0x52: /* fcmpd, V9 %fcc */
2850 gen_op_load_fpr_DT0(DFPREG(rs1));
2851 gen_op_load_fpr_DT1(DFPREG(rs2));
2852 gen_op_fcmpd(rd & 3);
2854 case 0x53: /* fcmpq, V9 %fcc */
2855 CHECK_FPU_FEATURE(dc, FLOAT128);
2856 gen_op_load_fpr_QT0(QFPREG(rs1));
2857 gen_op_load_fpr_QT1(QFPREG(rs2));
2858 gen_op_fcmpq(rd & 3);
2860 case 0x55: /* fcmpes, V9 %fcc */
2861 gen_op_load_fpr_FT0(rs1);
2862 gen_op_load_fpr_FT1(rs2);
2863 gen_op_fcmpes(rd & 3);
2865 case 0x56: /* fcmped, V9 %fcc */
2866 gen_op_load_fpr_DT0(DFPREG(rs1));
2867 gen_op_load_fpr_DT1(DFPREG(rs2));
2868 gen_op_fcmped(rd & 3);
2870 case 0x57: /* fcmpeq, V9 %fcc */
2871 CHECK_FPU_FEATURE(dc, FLOAT128);
2872 gen_op_load_fpr_QT0(QFPREG(rs1));
2873 gen_op_load_fpr_QT1(QFPREG(rs2));
2874 gen_op_fcmpeq(rd & 3);
2879 } else if (xop == 0x2) {
2882 rs1 = GET_FIELD(insn, 13, 17);
2884 // or %g0, x, y -> mov T0, x; mov y, T0
2885 if (IS_IMM) { /* immediate */
2888 rs2 = GET_FIELDs(insn, 19, 31);
2889 r_const = tcg_const_tl((int)rs2);
2890 gen_movl_TN_reg(rd, r_const);
2891 tcg_temp_free(r_const);
2892 } else { /* register */
2893 rs2 = GET_FIELD(insn, 27, 31);
2894 gen_movl_reg_TN(rs2, cpu_dst);
2895 gen_movl_TN_reg(rd, cpu_dst);
2898 cpu_src1 = get_src1(insn, cpu_src1);
2899 if (IS_IMM) { /* immediate */
2900 rs2 = GET_FIELDs(insn, 19, 31);
2901 tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2902 gen_movl_TN_reg(rd, cpu_dst);
2903 } else { /* register */
2904 // or x, %g0, y -> mov T1, x; mov y, T1
2905 rs2 = GET_FIELD(insn, 27, 31);
2907 gen_movl_reg_TN(rs2, cpu_src2);
2908 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2909 gen_movl_TN_reg(rd, cpu_dst);
2911 gen_movl_TN_reg(rd, cpu_src1);
2914 #ifdef TARGET_SPARC64
2915 } else if (xop == 0x25) { /* sll, V9 sllx */
2916 cpu_src1 = get_src1(insn, cpu_src1);
2917 if (IS_IMM) { /* immediate */
2918 rs2 = GET_FIELDs(insn, 20, 31);
2919 if (insn & (1 << 12)) {
2920 tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2922 tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
2924 } else { /* register */
2925 rs2 = GET_FIELD(insn, 27, 31);
2926 gen_movl_reg_TN(rs2, cpu_src2);
2927 if (insn & (1 << 12)) {
2928 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2930 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2932 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2934 gen_movl_TN_reg(rd, cpu_dst);
2935 } else if (xop == 0x26) { /* srl, V9 srlx */
2936 cpu_src1 = get_src1(insn, cpu_src1);
2937 if (IS_IMM) { /* immediate */
2938 rs2 = GET_FIELDs(insn, 20, 31);
2939 if (insn & (1 << 12)) {
2940 tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2942 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2943 tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2945 } else { /* register */
2946 rs2 = GET_FIELD(insn, 27, 31);
2947 gen_movl_reg_TN(rs2, cpu_src2);
2948 if (insn & (1 << 12)) {
2949 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2950 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2952 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2953 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2954 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2957 gen_movl_TN_reg(rd, cpu_dst);
2958 } else if (xop == 0x27) { /* sra, V9 srax */
2959 cpu_src1 = get_src1(insn, cpu_src1);
2960 if (IS_IMM) { /* immediate */
2961 rs2 = GET_FIELDs(insn, 20, 31);
2962 if (insn & (1 << 12)) {
2963 tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2965 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2966 tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2967 tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2969 } else { /* register */
2970 rs2 = GET_FIELD(insn, 27, 31);
2971 gen_movl_reg_TN(rs2, cpu_src2);
2972 if (insn & (1 << 12)) {
2973 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2974 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2976 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2977 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2978 tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2979 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2982 gen_movl_TN_reg(rd, cpu_dst);
2984 } else if (xop < 0x36) {
2985 cpu_src1 = get_src1(insn, cpu_src1);
2986 cpu_src2 = get_src2(insn, cpu_src2);
2988 switch (xop & ~0x10) {
2991 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2993 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2996 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2998 gen_op_logic_cc(cpu_dst);
3001 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3003 gen_op_logic_cc(cpu_dst);
3006 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3008 gen_op_logic_cc(cpu_dst);
3012 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3014 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3017 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3018 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3020 gen_op_logic_cc(cpu_dst);
3023 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3024 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3026 gen_op_logic_cc(cpu_dst);
3029 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3030 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3032 gen_op_logic_cc(cpu_dst);
3036 gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3038 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3039 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3040 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3043 #ifdef TARGET_SPARC64
3044 case 0x9: /* V9 mulx */
3045 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3049 CHECK_IU_FEATURE(dc, MUL);
3050 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3052 gen_op_logic_cc(cpu_dst);
3055 CHECK_IU_FEATURE(dc, MUL);
3056 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3058 gen_op_logic_cc(cpu_dst);
3062 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3064 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3065 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3066 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3069 #ifdef TARGET_SPARC64
3070 case 0xd: /* V9 udivx */
3071 tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3072 tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3073 gen_trap_ifdivzero_tl(cpu_cc_src2);
3074 tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3078 CHECK_IU_FEATURE(dc, DIV);
3079 tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3082 gen_op_div_cc(cpu_dst);
3085 CHECK_IU_FEATURE(dc, DIV);
3086 tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3089 gen_op_div_cc(cpu_dst);
3094 gen_movl_TN_reg(rd, cpu_dst);
3097 case 0x20: /* taddcc */
3098 gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3099 gen_movl_TN_reg(rd, cpu_dst);
3101 case 0x21: /* tsubcc */
3102 gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3103 gen_movl_TN_reg(rd, cpu_dst);
3105 case 0x22: /* taddcctv */
3106 save_state(dc, cpu_cond);
3107 gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3108 gen_movl_TN_reg(rd, cpu_dst);
3110 case 0x23: /* tsubcctv */
3111 save_state(dc, cpu_cond);
3112 gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3113 gen_movl_TN_reg(rd, cpu_dst);
3115 case 0x24: /* mulscc */
3116 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3117 gen_movl_TN_reg(rd, cpu_dst);
3119 #ifndef TARGET_SPARC64
3120 case 0x25: /* sll */
3121 if (IS_IMM) { /* immediate */
3122 rs2 = GET_FIELDs(insn, 20, 31);
3123 tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3124 } else { /* register */
3125 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3126 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3128 gen_movl_TN_reg(rd, cpu_dst);
3130 case 0x26: /* srl */
3131 if (IS_IMM) { /* immediate */
3132 rs2 = GET_FIELDs(insn, 20, 31);
3133 tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3134 } else { /* register */
3135 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3136 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3138 gen_movl_TN_reg(rd, cpu_dst);
3140 case 0x27: /* sra */
3141 if (IS_IMM) { /* immediate */
3142 rs2 = GET_FIELDs(insn, 20, 31);
3143 tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3144 } else { /* register */
3145 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3146 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3148 gen_movl_TN_reg(rd, cpu_dst);
3155 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3156 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3157 offsetof(CPUSPARCState, y));
3159 #ifndef TARGET_SPARC64
3160 case 0x01 ... 0x0f: /* undefined in the
3164 case 0x10 ... 0x1f: /* implementation-dependent
3170 case 0x2: /* V9 wrccr */
3171 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3172 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3174 case 0x3: /* V9 wrasi */
3175 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3176 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3177 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3178 offsetof(CPUSPARCState, asi));
3180 case 0x6: /* V9 wrfprs */
3181 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3182 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3183 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3184 offsetof(CPUSPARCState, fprs));
3185 save_state(dc, cpu_cond);
3190 case 0xf: /* V9 sir, nop if user */
3191 #if !defined(CONFIG_USER_ONLY)
3196 case 0x13: /* Graphics Status */
3197 if (gen_trap_ifnofpu(dc, cpu_cond))
3199 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3200 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3201 offsetof(CPUSPARCState, gsr));
3203 case 0x17: /* Tick compare */
3204 #if !defined(CONFIG_USER_ONLY)
3205 if (!supervisor(dc))
3211 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3213 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3214 offsetof(CPUSPARCState,
3216 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3217 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3218 offsetof(CPUState, tick));
3219 tcg_gen_helper_0_2(helper_tick_set_limit,
3220 r_tickptr, cpu_tmp0);
3221 tcg_temp_free(r_tickptr);
3224 case 0x18: /* System tick */
3225 #if !defined(CONFIG_USER_ONLY)
3226 if (!supervisor(dc))
3232 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3234 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3235 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3236 offsetof(CPUState, stick));
3237 tcg_gen_helper_0_2(helper_tick_set_count,
3238 r_tickptr, cpu_dst);
3239 tcg_temp_free(r_tickptr);
3242 case 0x19: /* System tick compare */
3243 #if !defined(CONFIG_USER_ONLY)
3244 if (!supervisor(dc))
3250 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3252 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3253 offsetof(CPUSPARCState,
3255 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3256 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3257 offsetof(CPUState, stick));
3258 tcg_gen_helper_0_2(helper_tick_set_limit,
3259 r_tickptr, cpu_tmp0);
3260 tcg_temp_free(r_tickptr);
3264 case 0x10: /* Performance Control */
3265 case 0x11: /* Performance Instrumentation
3267 case 0x12: /* Dispatch Control */
3268 case 0x14: /* Softint set */
3269 case 0x15: /* Softint clear */
3270 case 0x16: /* Softint write */
3277 #if !defined(CONFIG_USER_ONLY)
3278 case 0x31: /* wrpsr, V9 saved, restored */
3280 if (!supervisor(dc))
3282 #ifdef TARGET_SPARC64
3285 tcg_gen_helper_0_0(helper_saved);
3288 tcg_gen_helper_0_0(helper_restored);
3290 case 2: /* UA2005 allclean */
3291 case 3: /* UA2005 otherw */
3292 case 4: /* UA2005 normalw */
3293 case 5: /* UA2005 invalw */
3299 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3300 tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3301 save_state(dc, cpu_cond);
3308 case 0x32: /* wrwim, V9 wrpr */
3310 if (!supervisor(dc))
3312 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3313 #ifdef TARGET_SPARC64
3319 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3320 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3321 offsetof(CPUState, tsptr));
3322 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3323 offsetof(trap_state, tpc));
3324 tcg_temp_free(r_tsptr);
3331 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3332 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3333 offsetof(CPUState, tsptr));
3334 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3335 offsetof(trap_state, tnpc));
3336 tcg_temp_free(r_tsptr);
3343 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3344 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3345 offsetof(CPUState, tsptr));
3346 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3347 offsetof(trap_state,
3349 tcg_temp_free(r_tsptr);
3356 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3357 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3358 offsetof(CPUState, tsptr));
3359 tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3360 offsetof(trap_state, tt));
3361 tcg_temp_free(r_tsptr);
3368 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3369 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3370 offsetof(CPUState, tick));
3371 tcg_gen_helper_0_2(helper_tick_set_count,
3372 r_tickptr, cpu_tmp0);
3373 tcg_temp_free(r_tickptr);
3377 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3378 offsetof(CPUSPARCState, tbr));
3381 save_state(dc, cpu_cond);
3382 tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3388 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3389 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3390 offsetof(CPUSPARCState, tl));
3393 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3394 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3395 offsetof(CPUSPARCState,
3399 tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3402 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3403 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3404 offsetof(CPUSPARCState,
3407 case 11: // canrestore
3408 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3409 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3410 offsetof(CPUSPARCState,
3413 case 12: // cleanwin
3414 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3415 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3416 offsetof(CPUSPARCState,
3419 case 13: // otherwin
3420 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3421 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3422 offsetof(CPUSPARCState,
3426 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3427 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3428 offsetof(CPUSPARCState,
3431 case 16: // UA2005 gl
3432 CHECK_IU_FEATURE(dc, GL);
3433 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3434 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3435 offsetof(CPUSPARCState, gl));
3437 case 26: // UA2005 strand status
3438 CHECK_IU_FEATURE(dc, HYPV);
3439 if (!hypervisor(dc))
3441 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3442 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3443 offsetof(CPUSPARCState, ssr));
3449 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3450 if (dc->def->nwindows != 32)
3451 tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
3452 (1 << dc->def->nwindows) - 1);
3453 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3454 offsetof(CPUSPARCState, wim));
3458 case 0x33: /* wrtbr, UA2005 wrhpr */
3460 #ifndef TARGET_SPARC64
3461 if (!supervisor(dc))
3463 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3464 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3465 offsetof(CPUSPARCState, tbr));
3467 CHECK_IU_FEATURE(dc, HYPV);
3468 if (!hypervisor(dc))
3470 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3473 // XXX gen_op_wrhpstate();
3474 save_state(dc, cpu_cond);
3480 // XXX gen_op_wrhtstate();
3483 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3484 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3485 offsetof(CPUSPARCState, hintp));
3488 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3489 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3490 offsetof(CPUSPARCState, htba));
3492 case 31: // hstick_cmpr
3496 tcg_gen_st_tl(cpu_tmp0, cpu_env,
3497 offsetof(CPUSPARCState,
3499 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3500 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3501 offsetof(CPUState, hstick));
3502 tcg_gen_helper_0_2(helper_tick_set_limit,
3503 r_tickptr, cpu_tmp0);
3504 tcg_temp_free(r_tickptr);
3507 case 6: // hver readonly
3515 #ifdef TARGET_SPARC64
3516 case 0x2c: /* V9 movcc */
3518 int cc = GET_FIELD_SP(insn, 11, 12);
3519 int cond = GET_FIELD_SP(insn, 14, 17);
3523 r_cond = tcg_temp_new(TCG_TYPE_TL);
3524 if (insn & (1 << 18)) {
3526 gen_cond(r_cond, 0, cond);
3528 gen_cond(r_cond, 1, cond);
3532 gen_fcond(r_cond, cc, cond);
3535 l1 = gen_new_label();
3537 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3538 if (IS_IMM) { /* immediate */
3541 rs2 = GET_FIELD_SPs(insn, 0, 10);
3542 r_const = tcg_const_tl((int)rs2);
3543 gen_movl_TN_reg(rd, r_const);
3544 tcg_temp_free(r_const);
3546 rs2 = GET_FIELD_SP(insn, 0, 4);
3547 gen_movl_reg_TN(rs2, cpu_tmp0);
3548 gen_movl_TN_reg(rd, cpu_tmp0);
3551 tcg_temp_free(r_cond);
3554 case 0x2d: /* V9 sdivx */
3555 gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3556 gen_movl_TN_reg(rd, cpu_dst);
3558 case 0x2e: /* V9 popc */
3560 cpu_src2 = get_src2(insn, cpu_src2);
3561 tcg_gen_helper_1_1(helper_popc, cpu_dst,
3563 gen_movl_TN_reg(rd, cpu_dst);
3565 case 0x2f: /* V9 movr */
3567 int cond = GET_FIELD_SP(insn, 10, 12);
3570 cpu_src1 = get_src1(insn, cpu_src1);
3572 l1 = gen_new_label();
3574 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3576 if (IS_IMM) { /* immediate */
3579 rs2 = GET_FIELD_SPs(insn, 0, 9);
3580 r_const = tcg_const_tl((int)rs2);
3581 gen_movl_TN_reg(rd, r_const);
3582 tcg_temp_free(r_const);
3584 rs2 = GET_FIELD_SP(insn, 0, 4);
3585 gen_movl_reg_TN(rs2, cpu_tmp0);
3586 gen_movl_TN_reg(rd, cpu_tmp0);
3596 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3597 #ifdef TARGET_SPARC64
3598 int opf = GET_FIELD_SP(insn, 5, 13);
3599 rs1 = GET_FIELD(insn, 13, 17);
3600 rs2 = GET_FIELD(insn, 27, 31);
3601 if (gen_trap_ifnofpu(dc, cpu_cond))
3605 case 0x000: /* VIS I edge8cc */
3606 case 0x001: /* VIS II edge8n */
3607 case 0x002: /* VIS I edge8lcc */
3608 case 0x003: /* VIS II edge8ln */
3609 case 0x004: /* VIS I edge16cc */
3610 case 0x005: /* VIS II edge16n */
3611 case 0x006: /* VIS I edge16lcc */
3612 case 0x007: /* VIS II edge16ln */
3613 case 0x008: /* VIS I edge32cc */
3614 case 0x009: /* VIS II edge32n */
3615 case 0x00a: /* VIS I edge32lcc */
3616 case 0x00b: /* VIS II edge32ln */
3619 case 0x010: /* VIS I array8 */
3620 CHECK_FPU_FEATURE(dc, VIS1);
3621 cpu_src1 = get_src1(insn, cpu_src1);
3622 gen_movl_reg_TN(rs2, cpu_src2);
3623 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3625 gen_movl_TN_reg(rd, cpu_dst);
3627 case 0x012: /* VIS I array16 */
3628 CHECK_FPU_FEATURE(dc, VIS1);
3629 cpu_src1 = get_src1(insn, cpu_src1);
3630 gen_movl_reg_TN(rs2, cpu_src2);
3631 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3633 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3634 gen_movl_TN_reg(rd, cpu_dst);
3636 case 0x014: /* VIS I array32 */
3637 CHECK_FPU_FEATURE(dc, VIS1);
3638 cpu_src1 = get_src1(insn, cpu_src1);
3639 gen_movl_reg_TN(rs2, cpu_src2);
3640 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3642 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3643 gen_movl_TN_reg(rd, cpu_dst);
3645 case 0x018: /* VIS I alignaddr */
3646 CHECK_FPU_FEATURE(dc, VIS1);
3647 cpu_src1 = get_src1(insn, cpu_src1);
3648 gen_movl_reg_TN(rs2, cpu_src2);
3649 tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3651 gen_movl_TN_reg(rd, cpu_dst);
3653 case 0x019: /* VIS II bmask */
3654 case 0x01a: /* VIS I alignaddrl */
3657 case 0x020: /* VIS I fcmple16 */
3658 CHECK_FPU_FEATURE(dc, VIS1);
3659 gen_op_load_fpr_DT0(DFPREG(rs1));
3660 gen_op_load_fpr_DT1(DFPREG(rs2));
3661 tcg_gen_helper_0_0(helper_fcmple16);
3662 gen_op_store_DT0_fpr(DFPREG(rd));
3664 case 0x022: /* VIS I fcmpne16 */
3665 CHECK_FPU_FEATURE(dc, VIS1);
3666 gen_op_load_fpr_DT0(DFPREG(rs1));
3667 gen_op_load_fpr_DT1(DFPREG(rs2));
3668 tcg_gen_helper_0_0(helper_fcmpne16);
3669 gen_op_store_DT0_fpr(DFPREG(rd));
3671 case 0x024: /* VIS I fcmple32 */
3672 CHECK_FPU_FEATURE(dc, VIS1);
3673 gen_op_load_fpr_DT0(DFPREG(rs1));
3674 gen_op_load_fpr_DT1(DFPREG(rs2));
3675 tcg_gen_helper_0_0(helper_fcmple32);
3676 gen_op_store_DT0_fpr(DFPREG(rd));
3678 case 0x026: /* VIS I fcmpne32 */
3679 CHECK_FPU_FEATURE(dc, VIS1);
3680 gen_op_load_fpr_DT0(DFPREG(rs1));
3681 gen_op_load_fpr_DT1(DFPREG(rs2));
3682 tcg_gen_helper_0_0(helper_fcmpne32);
3683 gen_op_store_DT0_fpr(DFPREG(rd));
3685 case 0x028: /* VIS I fcmpgt16 */
3686 CHECK_FPU_FEATURE(dc, VIS1);
3687 gen_op_load_fpr_DT0(DFPREG(rs1));
3688 gen_op_load_fpr_DT1(DFPREG(rs2));
3689 tcg_gen_helper_0_0(helper_fcmpgt16);
3690 gen_op_store_DT0_fpr(DFPREG(rd));
3692 case 0x02a: /* VIS I fcmpeq16 */
3693 CHECK_FPU_FEATURE(dc, VIS1);
3694 gen_op_load_fpr_DT0(DFPREG(rs1));
3695 gen_op_load_fpr_DT1(DFPREG(rs2));
3696 tcg_gen_helper_0_0(helper_fcmpeq16);
3697 gen_op_store_DT0_fpr(DFPREG(rd));
3699 case 0x02c: /* VIS I fcmpgt32 */
3700 CHECK_FPU_FEATURE(dc, VIS1);
3701 gen_op_load_fpr_DT0(DFPREG(rs1));
3702 gen_op_load_fpr_DT1(DFPREG(rs2));
3703 tcg_gen_helper_0_0(helper_fcmpgt32);
3704 gen_op_store_DT0_fpr(DFPREG(rd));
3706 case 0x02e: /* VIS I fcmpeq32 */
3707 CHECK_FPU_FEATURE(dc, VIS1);
3708 gen_op_load_fpr_DT0(DFPREG(rs1));
3709 gen_op_load_fpr_DT1(DFPREG(rs2));
3710 tcg_gen_helper_0_0(helper_fcmpeq32);
3711 gen_op_store_DT0_fpr(DFPREG(rd));
3713 case 0x031: /* VIS I fmul8x16 */
3714 CHECK_FPU_FEATURE(dc, VIS1);
3715 gen_op_load_fpr_DT0(DFPREG(rs1));
3716 gen_op_load_fpr_DT1(DFPREG(rs2));
3717 tcg_gen_helper_0_0(helper_fmul8x16);
3718 gen_op_store_DT0_fpr(DFPREG(rd));
3720 case 0x033: /* VIS I fmul8x16au */
3721 CHECK_FPU_FEATURE(dc, VIS1);
3722 gen_op_load_fpr_DT0(DFPREG(rs1));
3723 gen_op_load_fpr_DT1(DFPREG(rs2));
3724 tcg_gen_helper_0_0(helper_fmul8x16au);
3725 gen_op_store_DT0_fpr(DFPREG(rd));
3727 case 0x035: /* VIS I fmul8x16al */
3728 CHECK_FPU_FEATURE(dc, VIS1);
3729 gen_op_load_fpr_DT0(DFPREG(rs1));
3730 gen_op_load_fpr_DT1(DFPREG(rs2));
3731 tcg_gen_helper_0_0(helper_fmul8x16al);
3732 gen_op_store_DT0_fpr(DFPREG(rd));
3734 case 0x036: /* VIS I fmul8sux16 */
3735 CHECK_FPU_FEATURE(dc, VIS1);
3736 gen_op_load_fpr_DT0(DFPREG(rs1));
3737 gen_op_load_fpr_DT1(DFPREG(rs2));
3738 tcg_gen_helper_0_0(helper_fmul8sux16);
3739 gen_op_store_DT0_fpr(DFPREG(rd));
3741 case 0x037: /* VIS I fmul8ulx16 */
3742 CHECK_FPU_FEATURE(dc, VIS1);
3743 gen_op_load_fpr_DT0(DFPREG(rs1));
3744 gen_op_load_fpr_DT1(DFPREG(rs2));
3745 tcg_gen_helper_0_0(helper_fmul8ulx16);
3746 gen_op_store_DT0_fpr(DFPREG(rd));
3748 case 0x038: /* VIS I fmuld8sux16 */
3749 CHECK_FPU_FEATURE(dc, VIS1);
3750 gen_op_load_fpr_DT0(DFPREG(rs1));
3751 gen_op_load_fpr_DT1(DFPREG(rs2));
3752 tcg_gen_helper_0_0(helper_fmuld8sux16);
3753 gen_op_store_DT0_fpr(DFPREG(rd));
3755 case 0x039: /* VIS I fmuld8ulx16 */
3756 CHECK_FPU_FEATURE(dc, VIS1);
3757 gen_op_load_fpr_DT0(DFPREG(rs1));
3758 gen_op_load_fpr_DT1(DFPREG(rs2));
3759 tcg_gen_helper_0_0(helper_fmuld8ulx16);
3760 gen_op_store_DT0_fpr(DFPREG(rd));
3762 case 0x03a: /* VIS I fpack32 */
3763 case 0x03b: /* VIS I fpack16 */
3764 case 0x03d: /* VIS I fpackfix */
3765 case 0x03e: /* VIS I pdist */
3768 case 0x048: /* VIS I faligndata */
3769 CHECK_FPU_FEATURE(dc, VIS1);
3770 gen_op_load_fpr_DT0(DFPREG(rs1));
3771 gen_op_load_fpr_DT1(DFPREG(rs2));
3772 tcg_gen_helper_0_0(helper_faligndata);
3773 gen_op_store_DT0_fpr(DFPREG(rd));
3775 case 0x04b: /* VIS I fpmerge */
3776 CHECK_FPU_FEATURE(dc, VIS1);
3777 gen_op_load_fpr_DT0(DFPREG(rs1));
3778 gen_op_load_fpr_DT1(DFPREG(rs2));
3779 tcg_gen_helper_0_0(helper_fpmerge);
3780 gen_op_store_DT0_fpr(DFPREG(rd));
3782 case 0x04c: /* VIS II bshuffle */
3785 case 0x04d: /* VIS I fexpand */
3786 CHECK_FPU_FEATURE(dc, VIS1);
3787 gen_op_load_fpr_DT0(DFPREG(rs1));
3788 gen_op_load_fpr_DT1(DFPREG(rs2));
3789 tcg_gen_helper_0_0(helper_fexpand);
3790 gen_op_store_DT0_fpr(DFPREG(rd));
3792 case 0x050: /* VIS I fpadd16 */
3793 CHECK_FPU_FEATURE(dc, VIS1);
3794 gen_op_load_fpr_DT0(DFPREG(rs1));
3795 gen_op_load_fpr_DT1(DFPREG(rs2));
3796 tcg_gen_helper_0_0(helper_fpadd16);
3797 gen_op_store_DT0_fpr(DFPREG(rd));
3799 case 0x051: /* VIS I fpadd16s */
3800 CHECK_FPU_FEATURE(dc, VIS1);
3801 gen_op_load_fpr_FT0(rs1);
3802 gen_op_load_fpr_FT1(rs2);
3803 tcg_gen_helper_0_0(helper_fpadd16s);
3804 gen_op_store_FT0_fpr(rd);
3806 case 0x052: /* VIS I fpadd32 */
3807 CHECK_FPU_FEATURE(dc, VIS1);
3808 gen_op_load_fpr_DT0(DFPREG(rs1));
3809 gen_op_load_fpr_DT1(DFPREG(rs2));
3810 tcg_gen_helper_0_0(helper_fpadd32);
3811 gen_op_store_DT0_fpr(DFPREG(rd));
3813 case 0x053: /* VIS I fpadd32s */
3814 CHECK_FPU_FEATURE(dc, VIS1);
3815 gen_op_load_fpr_FT0(rs1);
3816 gen_op_load_fpr_FT1(rs2);
3817 tcg_gen_helper_0_0(helper_fpadd32s);
3818 gen_op_store_FT0_fpr(rd);
3820 case 0x054: /* VIS I fpsub16 */
3821 CHECK_FPU_FEATURE(dc, VIS1);
3822 gen_op_load_fpr_DT0(DFPREG(rs1));
3823 gen_op_load_fpr_DT1(DFPREG(rs2));
3824 tcg_gen_helper_0_0(helper_fpsub16);
3825 gen_op_store_DT0_fpr(DFPREG(rd));
3827 case 0x055: /* VIS I fpsub16s */
3828 CHECK_FPU_FEATURE(dc, VIS1);
3829 gen_op_load_fpr_FT0(rs1);
3830 gen_op_load_fpr_FT1(rs2);
3831 tcg_gen_helper_0_0(helper_fpsub16s);
3832 gen_op_store_FT0_fpr(rd);
3834 case 0x056: /* VIS I fpsub32 */
3835 CHECK_FPU_FEATURE(dc, VIS1);
3836 gen_op_load_fpr_DT0(DFPREG(rs1));
3837 gen_op_load_fpr_DT1(DFPREG(rs2));
3838 tcg_gen_helper_0_0(helper_fpadd32);
3839 gen_op_store_DT0_fpr(DFPREG(rd));
3841 case 0x057: /* VIS I fpsub32s */
3842 CHECK_FPU_FEATURE(dc, VIS1);
3843 gen_op_load_fpr_FT0(rs1);
3844 gen_op_load_fpr_FT1(rs2);
3845 tcg_gen_helper_0_0(helper_fpsub32s);
3846 gen_op_store_FT0_fpr(rd);
3848 case 0x060: /* VIS I fzero */
3849 CHECK_FPU_FEATURE(dc, VIS1);
3850 tcg_gen_helper_0_0(helper_movl_DT0_0);
3851 gen_op_store_DT0_fpr(DFPREG(rd));
3853 case 0x061: /* VIS I fzeros */
3854 CHECK_FPU_FEATURE(dc, VIS1);
3855 tcg_gen_helper_0_0(helper_movl_FT0_0);
3856 gen_op_store_FT0_fpr(rd);
3858 case 0x062: /* VIS I fnor */
3859 CHECK_FPU_FEATURE(dc, VIS1);
3860 gen_op_load_fpr_DT0(DFPREG(rs1));
3861 gen_op_load_fpr_DT1(DFPREG(rs2));
3862 tcg_gen_helper_0_0(helper_fnor);
3863 gen_op_store_DT0_fpr(DFPREG(rd));
3865 case 0x063: /* VIS I fnors */
3866 CHECK_FPU_FEATURE(dc, VIS1);
3867 gen_op_load_fpr_FT0(rs1);
3868 gen_op_load_fpr_FT1(rs2);
3869 tcg_gen_helper_0_0(helper_fnors);
3870 gen_op_store_FT0_fpr(rd);
3872 case 0x064: /* VIS I fandnot2 */
3873 CHECK_FPU_FEATURE(dc, VIS1);
3874 gen_op_load_fpr_DT1(DFPREG(rs1));
3875 gen_op_load_fpr_DT0(DFPREG(rs2));
3876 tcg_gen_helper_0_0(helper_fandnot);
3877 gen_op_store_DT0_fpr(DFPREG(rd));
3879 case 0x065: /* VIS I fandnot2s */
3880 CHECK_FPU_FEATURE(dc, VIS1);
3881 gen_op_load_fpr_FT1(rs1);
3882 gen_op_load_fpr_FT0(rs2);
3883 tcg_gen_helper_0_0(helper_fandnots);
3884 gen_op_store_FT0_fpr(rd);
3886 case 0x066: /* VIS I fnot2 */
3887 CHECK_FPU_FEATURE(dc, VIS1);
3888 gen_op_load_fpr_DT1(DFPREG(rs2));
3889 tcg_gen_helper_0_0(helper_fnot);
3890 gen_op_store_DT0_fpr(DFPREG(rd));
3892 case 0x067: /* VIS I fnot2s */
3893 CHECK_FPU_FEATURE(dc, VIS1);
3894 gen_op_load_fpr_FT1(rs2);
3895 tcg_gen_helper_0_0(helper_fnot);
3896 gen_op_store_FT0_fpr(rd);
3898 case 0x068: /* VIS I fandnot1 */
3899 CHECK_FPU_FEATURE(dc, VIS1);
3900 gen_op_load_fpr_DT0(DFPREG(rs1));
3901 gen_op_load_fpr_DT1(DFPREG(rs2));
3902 tcg_gen_helper_0_0(helper_fandnot);
3903 gen_op_store_DT0_fpr(DFPREG(rd));
3905 case 0x069: /* VIS I fandnot1s */
3906 CHECK_FPU_FEATURE(dc, VIS1);
3907 gen_op_load_fpr_FT0(rs1);
3908 gen_op_load_fpr_FT1(rs2);
3909 tcg_gen_helper_0_0(helper_fandnots);
3910 gen_op_store_FT0_fpr(rd);
3912 case 0x06a: /* VIS I fnot1 */
3913 CHECK_FPU_FEATURE(dc, VIS1);
3914 gen_op_load_fpr_DT1(DFPREG(rs1));
3915 tcg_gen_helper_0_0(helper_fnot);
3916 gen_op_store_DT0_fpr(DFPREG(rd));
3918 case 0x06b: /* VIS I fnot1s */
3919 CHECK_FPU_FEATURE(dc, VIS1);
3920 gen_op_load_fpr_FT1(rs1);
3921 tcg_gen_helper_0_0(helper_fnot);
3922 gen_op_store_FT0_fpr(rd);
3924 case 0x06c: /* VIS I fxor */
3925 CHECK_FPU_FEATURE(dc, VIS1);
3926 gen_op_load_fpr_DT0(DFPREG(rs1));
3927 gen_op_load_fpr_DT1(DFPREG(rs2));
3928 tcg_gen_helper_0_0(helper_fxor);
3929 gen_op_store_DT0_fpr(DFPREG(rd));
3931 case 0x06d: /* VIS I fxors */
3932 CHECK_FPU_FEATURE(dc, VIS1);
3933 gen_op_load_fpr_FT0(rs1);
3934 gen_op_load_fpr_FT1(rs2);
3935 tcg_gen_helper_0_0(helper_fxors);
3936 gen_op_store_FT0_fpr(rd);
3938 case 0x06e: /* VIS I fnand */
3939 CHECK_FPU_FEATURE(dc, VIS1);
3940 gen_op_load_fpr_DT0(DFPREG(rs1));
3941 gen_op_load_fpr_DT1(DFPREG(rs2));
3942 tcg_gen_helper_0_0(helper_fnand);
3943 gen_op_store_DT0_fpr(DFPREG(rd));
3945 case 0x06f: /* VIS I fnands */
3946 CHECK_FPU_FEATURE(dc, VIS1);
3947 gen_op_load_fpr_FT0(rs1);
3948 gen_op_load_fpr_FT1(rs2);
3949 tcg_gen_helper_0_0(helper_fnands);
3950 gen_op_store_FT0_fpr(rd);
3952 case 0x070: /* VIS I fand */
3953 CHECK_FPU_FEATURE(dc, VIS1);
3954 gen_op_load_fpr_DT0(DFPREG(rs1));
3955 gen_op_load_fpr_DT1(DFPREG(rs2));
3956 tcg_gen_helper_0_0(helper_fand);
3957 gen_op_store_DT0_fpr(DFPREG(rd));
3959 case 0x071: /* VIS I fands */
3960 CHECK_FPU_FEATURE(dc, VIS1);
3961 gen_op_load_fpr_FT0(rs1);
3962 gen_op_load_fpr_FT1(rs2);
3963 tcg_gen_helper_0_0(helper_fands);
3964 gen_op_store_FT0_fpr(rd);
3966 case 0x072: /* VIS I fxnor */
3967 CHECK_FPU_FEATURE(dc, VIS1);
3968 gen_op_load_fpr_DT0(DFPREG(rs1));
3969 gen_op_load_fpr_DT1(DFPREG(rs2));
3970 tcg_gen_helper_0_0(helper_fxnor);
3971 gen_op_store_DT0_fpr(DFPREG(rd));
3973 case 0x073: /* VIS I fxnors */
3974 CHECK_FPU_FEATURE(dc, VIS1);
3975 gen_op_load_fpr_FT0(rs1);
3976 gen_op_load_fpr_FT1(rs2);
3977 tcg_gen_helper_0_0(helper_fxnors);
3978 gen_op_store_FT0_fpr(rd);
3980 case 0x074: /* VIS I fsrc1 */
3981 CHECK_FPU_FEATURE(dc, VIS1);
3982 gen_op_load_fpr_DT0(DFPREG(rs1));
3983 gen_op_store_DT0_fpr(DFPREG(rd));
3985 case 0x075: /* VIS I fsrc1s */
3986 CHECK_FPU_FEATURE(dc, VIS1);
3987 gen_op_load_fpr_FT0(rs1);
3988 gen_op_store_FT0_fpr(rd);
3990 case 0x076: /* VIS I fornot2 */
3991 CHECK_FPU_FEATURE(dc, VIS1);
3992 gen_op_load_fpr_DT1(DFPREG(rs1));
3993 gen_op_load_fpr_DT0(DFPREG(rs2));
3994 tcg_gen_helper_0_0(helper_fornot);
3995 gen_op_store_DT0_fpr(DFPREG(rd));
3997 case 0x077: /* VIS I fornot2s */
3998 CHECK_FPU_FEATURE(dc, VIS1);
3999 gen_op_load_fpr_FT1(rs1);
4000 gen_op_load_fpr_FT0(rs2);
4001 tcg_gen_helper_0_0(helper_fornots);
4002 gen_op_store_FT0_fpr(rd);
4004 case 0x078: /* VIS I fsrc2 */
4005 CHECK_FPU_FEATURE(dc, VIS1);
4006 gen_op_load_fpr_DT0(DFPREG(rs2));
4007 gen_op_store_DT0_fpr(DFPREG(rd));
4009 case 0x079: /* VIS I fsrc2s */
4010 CHECK_FPU_FEATURE(dc, VIS1);
4011 gen_op_load_fpr_FT0(rs2);
4012 gen_op_store_FT0_fpr(rd);
4014 case 0x07a: /* VIS I fornot1 */
4015 CHECK_FPU_FEATURE(dc, VIS1);
4016 gen_op_load_fpr_DT0(DFPREG(rs1));
4017 gen_op_load_fpr_DT1(DFPREG(rs2));
4018 tcg_gen_helper_0_0(helper_fornot);
4019 gen_op_store_DT0_fpr(DFPREG(rd));
4021 case 0x07b: /* VIS I fornot1s */
4022 CHECK_FPU_FEATURE(dc, VIS1);
4023 gen_op_load_fpr_FT0(rs1);
4024 gen_op_load_fpr_FT1(rs2);
4025 tcg_gen_helper_0_0(helper_fornots);
4026 gen_op_store_FT0_fpr(rd);
4028 case 0x07c: /* VIS I for */
4029 CHECK_FPU_FEATURE(dc, VIS1);
4030 gen_op_load_fpr_DT0(DFPREG(rs1));
4031 gen_op_load_fpr_DT1(DFPREG(rs2));
4032 tcg_gen_helper_0_0(helper_for);
4033 gen_op_store_DT0_fpr(DFPREG(rd));
4035 case 0x07d: /* VIS I fors */
4036 CHECK_FPU_FEATURE(dc, VIS1);
4037 gen_op_load_fpr_FT0(rs1);
4038 gen_op_load_fpr_FT1(rs2);
4039 tcg_gen_helper_0_0(helper_fors);
4040 gen_op_store_FT0_fpr(rd);
4042 case 0x07e: /* VIS I fone */
4043 CHECK_FPU_FEATURE(dc, VIS1);
4044 tcg_gen_helper_0_0(helper_movl_DT0_1);
4045 gen_op_store_DT0_fpr(DFPREG(rd));
4047 case 0x07f: /* VIS I fones */
4048 CHECK_FPU_FEATURE(dc, VIS1);
4049 tcg_gen_helper_0_0(helper_movl_FT0_1);
4050 gen_op_store_FT0_fpr(rd);
4052 case 0x080: /* VIS I shutdown */
4053 case 0x081: /* VIS II siam */
4062 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4063 #ifdef TARGET_SPARC64
4068 #ifdef TARGET_SPARC64
4069 } else if (xop == 0x39) { /* V9 return */
4072 save_state(dc, cpu_cond);
4073 cpu_src1 = get_src1(insn, cpu_src1);
4074 if (IS_IMM) { /* immediate */
4075 rs2 = GET_FIELDs(insn, 19, 31);
4076 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4077 } else { /* register */
4078 rs2 = GET_FIELD(insn, 27, 31);
4080 gen_movl_reg_TN(rs2, cpu_src2);
4081 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4083 tcg_gen_mov_tl(cpu_dst, cpu_src1);
4085 tcg_gen_helper_0_0(helper_restore);
4086 gen_mov_pc_npc(dc, cpu_cond);
4087 r_const = tcg_const_i32(3);
4088 tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4089 tcg_temp_free(r_const);
4090 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4091 dc->npc = DYNAMIC_PC;
4095 cpu_src1 = get_src1(insn, cpu_src1);
4096 if (IS_IMM) { /* immediate */
4097 rs2 = GET_FIELDs(insn, 19, 31);
4098 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4099 } else { /* register */
4100 rs2 = GET_FIELD(insn, 27, 31);
4102 gen_movl_reg_TN(rs2, cpu_src2);
4103 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4105 tcg_gen_mov_tl(cpu_dst, cpu_src1);
4108 case 0x38: /* jmpl */
4112 r_const = tcg_const_tl(dc->pc);
4113 gen_movl_TN_reg(rd, r_const);
4114 tcg_temp_free(r_const);
4115 gen_mov_pc_npc(dc, cpu_cond);
4116 r_const = tcg_const_i32(3);
4117 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4119 tcg_temp_free(r_const);
4120 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4121 dc->npc = DYNAMIC_PC;
4124 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4125 case 0x39: /* rett, V9 return */
4129 if (!supervisor(dc))
4131 gen_mov_pc_npc(dc, cpu_cond);
4132 r_const = tcg_const_i32(3);
4133 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4135 tcg_temp_free(r_const);
4136 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4137 dc->npc = DYNAMIC_PC;
4138 tcg_gen_helper_0_0(helper_rett);
4142 case 0x3b: /* flush */
4143 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
4145 tcg_gen_helper_0_1(helper_flush, cpu_dst);
4147 case 0x3c: /* save */
4148 save_state(dc, cpu_cond);
4149 tcg_gen_helper_0_0(helper_save);
4150 gen_movl_TN_reg(rd, cpu_dst);
4152 case 0x3d: /* restore */
4153 save_state(dc, cpu_cond);
4154 tcg_gen_helper_0_0(helper_restore);
4155 gen_movl_TN_reg(rd, cpu_dst);
4157 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4158 case 0x3e: /* V9 done/retry */
4162 if (!supervisor(dc))
4164 dc->npc = DYNAMIC_PC;
4165 dc->pc = DYNAMIC_PC;
4166 tcg_gen_helper_0_0(helper_done);
4169 if (!supervisor(dc))
4171 dc->npc = DYNAMIC_PC;
4172 dc->pc = DYNAMIC_PC;
4173 tcg_gen_helper_0_0(helper_retry);
4188 case 3: /* load/store instructions */
4190 unsigned int xop = GET_FIELD(insn, 7, 12);
4192 cpu_src1 = get_src1(insn, cpu_src1);
4193 if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
4194 rs2 = GET_FIELD(insn, 27, 31);
4195 gen_movl_reg_TN(rs2, cpu_src2);
4196 tcg_gen_mov_tl(cpu_addr, cpu_src1);
4197 } else if (IS_IMM) { /* immediate */
4198 rs2 = GET_FIELDs(insn, 19, 31);
4199 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4200 } else { /* register */
4201 rs2 = GET_FIELD(insn, 27, 31);
4203 gen_movl_reg_TN(rs2, cpu_src2);
4204 tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4206 tcg_gen_mov_tl(cpu_addr, cpu_src1);
4208 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4209 (xop > 0x17 && xop <= 0x1d ) ||
4210 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4212 case 0x0: /* load unsigned word */
4213 gen_address_mask(dc, cpu_addr);
4214 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4216 case 0x1: /* load unsigned byte */
4217 gen_address_mask(dc, cpu_addr);
4218 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4220 case 0x2: /* load unsigned halfword */
4221 gen_address_mask(dc, cpu_addr);
4222 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4224 case 0x3: /* load double word */
4230 save_state(dc, cpu_cond);
4231 r_const = tcg_const_i32(7);
4232 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4233 r_const); // XXX remove
4234 tcg_temp_free(r_const);
4235 gen_address_mask(dc, cpu_addr);
4236 tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4237 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4238 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4239 gen_movl_TN_reg(rd + 1, cpu_tmp0);
4240 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4241 tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4242 tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4245 case 0x9: /* load signed byte */
4246 gen_address_mask(dc, cpu_addr);
4247 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4249 case 0xa: /* load signed halfword */
4250 gen_address_mask(dc, cpu_addr);
4251 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4253 case 0xd: /* ldstub -- XXX: should be atomically */
4257 gen_address_mask(dc, cpu_addr);
4258 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4259 r_const = tcg_const_tl(0xff);
4260 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4261 tcg_temp_free(r_const);
4264 case 0x0f: /* swap register with memory. Also
4266 CHECK_IU_FEATURE(dc, SWAP);
4267 gen_movl_reg_TN(rd, cpu_val);
4268 gen_address_mask(dc, cpu_addr);
4269 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4270 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4271 tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4273 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4274 case 0x10: /* load word alternate */
4275 #ifndef TARGET_SPARC64
4278 if (!supervisor(dc))
4281 save_state(dc, cpu_cond);
4282 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4284 case 0x11: /* load unsigned byte alternate */
4285 #ifndef TARGET_SPARC64
4288 if (!supervisor(dc))
4291 save_state(dc, cpu_cond);
4292 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4294 case 0x12: /* load unsigned halfword alternate */
4295 #ifndef TARGET_SPARC64
4298 if (!supervisor(dc))
4301 save_state(dc, cpu_cond);
4302 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4304 case 0x13: /* load double word alternate */
4305 #ifndef TARGET_SPARC64
4308 if (!supervisor(dc))
4313 save_state(dc, cpu_cond);
4314 gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4316 case 0x19: /* load signed byte alternate */
4317 #ifndef TARGET_SPARC64
4320 if (!supervisor(dc))
4323 save_state(dc, cpu_cond);
4324 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4326 case 0x1a: /* load signed halfword alternate */
4327 #ifndef TARGET_SPARC64
4330 if (!supervisor(dc))
4333 save_state(dc, cpu_cond);
4334 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4336 case 0x1d: /* ldstuba -- XXX: should be atomically */
4337 #ifndef TARGET_SPARC64
4340 if (!supervisor(dc))
4343 save_state(dc, cpu_cond);
4344 gen_ldstub_asi(cpu_val, cpu_addr, insn);
4346 case 0x1f: /* swap reg with alt. memory. Also
4348 CHECK_IU_FEATURE(dc, SWAP);
4349 #ifndef TARGET_SPARC64
4352 if (!supervisor(dc))
4355 save_state(dc, cpu_cond);
4356 gen_movl_reg_TN(rd, cpu_val);
4357 gen_swap_asi(cpu_val, cpu_addr, insn);
4360 #ifndef TARGET_SPARC64
4361 case 0x30: /* ldc */
4362 case 0x31: /* ldcsr */
4363 case 0x33: /* lddc */
4367 #ifdef TARGET_SPARC64
4368 case 0x08: /* V9 ldsw */
4369 gen_address_mask(dc, cpu_addr);
4370 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4372 case 0x0b: /* V9 ldx */
4373 gen_address_mask(dc, cpu_addr);
4374 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4376 case 0x18: /* V9 ldswa */
4377 save_state(dc, cpu_cond);
4378 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4380 case 0x1b: /* V9 ldxa */
4381 save_state(dc, cpu_cond);
4382 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4384 case 0x2d: /* V9 prefetch, no effect */
4386 case 0x30: /* V9 ldfa */
4387 save_state(dc, cpu_cond);
4388 gen_ldf_asi(cpu_addr, insn, 4, rd);
4390 case 0x33: /* V9 lddfa */
4391 save_state(dc, cpu_cond);
4392 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4394 case 0x3d: /* V9 prefetcha, no effect */
4396 case 0x32: /* V9 ldqfa */
4397 CHECK_FPU_FEATURE(dc, FLOAT128);
4398 save_state(dc, cpu_cond);
4399 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4405 gen_movl_TN_reg(rd, cpu_val);
4406 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4409 } else if (xop >= 0x20 && xop < 0x24) {
4410 if (gen_trap_ifnofpu(dc, cpu_cond))
4412 save_state(dc, cpu_cond);
4414 case 0x20: /* load fpreg */
4415 gen_address_mask(dc, cpu_addr);
4416 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4417 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4418 offsetof(CPUState, fpr[rd]));
4420 case 0x21: /* load fsr */
4421 gen_address_mask(dc, cpu_addr);
4422 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4423 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4424 offsetof(CPUState, ft0));
4425 tcg_gen_helper_0_0(helper_ldfsr);
4427 case 0x22: /* load quad fpreg */
4431 CHECK_FPU_FEATURE(dc, FLOAT128);
4432 r_const = tcg_const_i32(dc->mem_idx);
4433 tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4434 tcg_temp_free(r_const);
4435 gen_op_store_QT0_fpr(QFPREG(rd));
4438 case 0x23: /* load double fpreg */
4442 r_const = tcg_const_i32(dc->mem_idx);
4443 tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4444 tcg_temp_free(r_const);
4445 gen_op_store_DT0_fpr(DFPREG(rd));
4451 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4452 xop == 0xe || xop == 0x1e) {
4453 gen_movl_reg_TN(rd, cpu_val);
4455 case 0x4: /* store word */
4456 gen_address_mask(dc, cpu_addr);
4457 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4459 case 0x5: /* store byte */
4460 gen_address_mask(dc, cpu_addr);
4461 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4463 case 0x6: /* store halfword */
4464 gen_address_mask(dc, cpu_addr);
4465 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4467 case 0x7: /* store double word */
4471 TCGv r_low, r_const;
4473 save_state(dc, cpu_cond);
4474 gen_address_mask(dc, cpu_addr);
4475 r_const = tcg_const_i32(7);
4476 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4477 r_const); // XXX remove
4478 tcg_temp_free(r_const);
4479 r_low = tcg_temp_new(TCG_TYPE_TL);
4480 gen_movl_reg_TN(rd + 1, r_low);
4481 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4483 tcg_temp_free(r_low);
4484 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4487 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4488 case 0x14: /* store word alternate */
4489 #ifndef TARGET_SPARC64
4492 if (!supervisor(dc))
4495 save_state(dc, cpu_cond);
4496 gen_st_asi(cpu_val, cpu_addr, insn, 4);
4498 case 0x15: /* store byte alternate */
4499 #ifndef TARGET_SPARC64
4502 if (!supervisor(dc))
4505 save_state(dc, cpu_cond);
4506 gen_st_asi(cpu_val, cpu_addr, insn, 1);
4508 case 0x16: /* store halfword alternate */
4509 #ifndef TARGET_SPARC64
4512 if (!supervisor(dc))
4515 save_state(dc, cpu_cond);
4516 gen_st_asi(cpu_val, cpu_addr, insn, 2);
4518 case 0x17: /* store double word alternate */
4519 #ifndef TARGET_SPARC64
4522 if (!supervisor(dc))
4528 save_state(dc, cpu_cond);
4529 gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4533 #ifdef TARGET_SPARC64
4534 case 0x0e: /* V9 stx */
4535 gen_address_mask(dc, cpu_addr);
4536 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4538 case 0x1e: /* V9 stxa */
4539 save_state(dc, cpu_cond);
4540 gen_st_asi(cpu_val, cpu_addr, insn, 8);
4546 } else if (xop > 0x23 && xop < 0x28) {
4547 if (gen_trap_ifnofpu(dc, cpu_cond))
4549 save_state(dc, cpu_cond);
4551 case 0x24: /* store fpreg */
4552 gen_address_mask(dc, cpu_addr);
4553 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4554 offsetof(CPUState, fpr[rd]));
4555 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4557 case 0x25: /* stfsr, V9 stxfsr */
4558 gen_address_mask(dc, cpu_addr);
4559 tcg_gen_helper_0_0(helper_stfsr);
4560 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4561 offsetof(CPUState, ft0));
4562 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4565 #ifdef TARGET_SPARC64
4566 /* V9 stqf, store quad fpreg */
4570 CHECK_FPU_FEATURE(dc, FLOAT128);
4571 gen_op_load_fpr_QT0(QFPREG(rd));
4572 r_const = tcg_const_i32(dc->mem_idx);
4573 tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4574 tcg_temp_free(r_const);
4577 #else /* !TARGET_SPARC64 */
4578 /* stdfq, store floating point queue */
4579 #if defined(CONFIG_USER_ONLY)
4582 if (!supervisor(dc))
4584 if (gen_trap_ifnofpu(dc, cpu_cond))
4589 case 0x27: /* store double fpreg */
4593 gen_op_load_fpr_DT0(DFPREG(rd));
4594 r_const = tcg_const_i32(dc->mem_idx);
4595 tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4596 tcg_temp_free(r_const);
4602 } else if (xop > 0x33 && xop < 0x3f) {
4603 save_state(dc, cpu_cond);
4605 #ifdef TARGET_SPARC64
4606 case 0x34: /* V9 stfa */
4607 gen_op_load_fpr_FT0(rd);
4608 gen_stf_asi(cpu_addr, insn, 4, rd);
4610 case 0x36: /* V9 stqfa */
4614 CHECK_FPU_FEATURE(dc, FLOAT128);
4615 r_const = tcg_const_i32(7);
4616 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4618 tcg_temp_free(r_const);
4619 gen_op_load_fpr_QT0(QFPREG(rd));
4620 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4623 case 0x37: /* V9 stdfa */
4624 gen_op_load_fpr_DT0(DFPREG(rd));
4625 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4627 case 0x3c: /* V9 casa */
4628 gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4629 gen_movl_TN_reg(rd, cpu_val);
4631 case 0x3e: /* V9 casxa */
4632 gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4633 gen_movl_TN_reg(rd, cpu_val);
4636 case 0x34: /* stc */
4637 case 0x35: /* stcsr */
4638 case 0x36: /* stdcq */
4639 case 0x37: /* stdc */
4651 /* default case for non jump instructions */
4652 if (dc->npc == DYNAMIC_PC) {
4653 dc->pc = DYNAMIC_PC;
4655 } else if (dc->npc == JUMP_PC) {
4656 /* we can do a static jump */
4657 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4661 dc->npc = dc->npc + 4;
4669 save_state(dc, cpu_cond);
4670 r_const = tcg_const_i32(TT_ILL_INSN);
4671 tcg_gen_helper_0_1(raise_exception, r_const);
4672 tcg_temp_free(r_const);
4680 save_state(dc, cpu_cond);
4681 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4682 tcg_gen_helper_0_1(raise_exception, r_const);
4683 tcg_temp_free(r_const);
4687 #if !defined(CONFIG_USER_ONLY)
4692 save_state(dc, cpu_cond);
4693 r_const = tcg_const_i32(TT_PRIV_INSN);
4694 tcg_gen_helper_0_1(raise_exception, r_const);
4695 tcg_temp_free(r_const);
4701 save_state(dc, cpu_cond);
4702 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4705 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4707 save_state(dc, cpu_cond);
4708 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4712 #ifndef TARGET_SPARC64
4717 save_state(dc, cpu_cond);
4718 r_const = tcg_const_i32(TT_NCP_INSN);
4719 tcg_gen_helper_0_1(raise_exception, r_const);
4720 tcg_temp_free(r_const);
4727 static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4728 int spc, CPUSPARCState *env)
4730 target_ulong pc_start, last_pc;
4731 uint16_t *gen_opc_end;
4732 DisasContext dc1, *dc = &dc1;
4737 memset(dc, 0, sizeof(DisasContext));
4742 dc->npc = (target_ulong) tb->cs_base;
4743 dc->mem_idx = cpu_mmu_index(env);
4745 if ((dc->def->features & CPU_FEATURE_FLOAT))
4746 dc->fpu_enabled = cpu_fpu_enabled(env);
4748 dc->fpu_enabled = 0;
4749 #ifdef TARGET_SPARC64
4750 dc->address_mask_32bit = env->pstate & PS_AM;
4752 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4754 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4755 cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4756 cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4758 cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4761 cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4762 cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4765 max_insns = tb->cflags & CF_COUNT_MASK;
4767 max_insns = CF_COUNT_MASK;
4770 if (env->nb_breakpoints > 0) {
4771 for(j = 0; j < env->nb_breakpoints; j++) {
4772 if (env->breakpoints[j] == dc->pc) {
4773 if (dc->pc != pc_start)
4774 save_state(dc, cpu_cond);
4775 tcg_gen_helper_0_0(helper_debug);
4784 fprintf(logfile, "Search PC...\n");
4785 j = gen_opc_ptr - gen_opc_buf;
4789 gen_opc_instr_start[lj++] = 0;
4790 gen_opc_pc[lj] = dc->pc;
4791 gen_opc_npc[lj] = dc->npc;
4792 gen_opc_instr_start[lj] = 1;
4793 gen_opc_icount[lj] = num_insns;
4796 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4799 disas_sparc_insn(dc);
4804 /* if the next PC is different, we abort now */
4805 if (dc->pc != (last_pc + 4))
4807 /* if we reach a page boundary, we stop generation so that the
4808 PC of a TT_TFAULT exception is always in the right page */
4809 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4811 /* if single step mode, we generate only one instruction and
4812 generate an exception */
4813 if (env->singlestep_enabled) {
4814 tcg_gen_movi_tl(cpu_pc, dc->pc);
4818 } while ((gen_opc_ptr < gen_opc_end) &&
4819 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4820 num_insns < max_insns);
4823 tcg_temp_free(cpu_addr);
4824 tcg_temp_free(cpu_val);
4825 tcg_temp_free(cpu_dst);
4826 tcg_temp_free(cpu_tmp64);
4827 tcg_temp_free(cpu_tmp32);
4828 tcg_temp_free(cpu_tmp0);
4829 if (tb->cflags & CF_LAST_IO)
4832 if (dc->pc != DYNAMIC_PC &&
4833 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4834 /* static PC and NPC: we can use direct chaining */
4835 gen_goto_tb(dc, 0, dc->pc, dc->npc);
4837 if (dc->pc != DYNAMIC_PC)
4838 tcg_gen_movi_tl(cpu_pc, dc->pc);
4839 save_npc(dc, cpu_cond);
4843 gen_icount_end(tb, num_insns);
4844 *gen_opc_ptr = INDEX_op_end;
4846 j = gen_opc_ptr - gen_opc_buf;
4849 gen_opc_instr_start[lj++] = 0;
4855 gen_opc_jump_pc[0] = dc->jump_pc[0];
4856 gen_opc_jump_pc[1] = dc->jump_pc[1];
4858 tb->size = last_pc + 4 - pc_start;
4859 tb->icount = num_insns;
4862 if (loglevel & CPU_LOG_TB_IN_ASM) {
4863 fprintf(logfile, "--------------\n");
4864 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4865 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4866 fprintf(logfile, "\n");
4871 void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4873 gen_intermediate_code_internal(tb, 0, env);
4876 void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4878 gen_intermediate_code_internal(tb, 1, env);
4881 void gen_intermediate_code_init(CPUSPARCState *env)
4885 static const char * const gregnames[8] = {
4886 NULL, // g0 not used
4896 /* init various static tables */
4900 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4901 cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4902 offsetof(CPUState, regwptr),
4904 #ifdef TARGET_SPARC64
4905 cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4906 TCG_AREG0, offsetof(CPUState, xcc),
4909 cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4910 TCG_AREG0, offsetof(CPUState, cond),
4912 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4913 TCG_AREG0, offsetof(CPUState, cc_src),
4915 cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4916 offsetof(CPUState, cc_src2),
4918 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4919 TCG_AREG0, offsetof(CPUState, cc_dst),
4921 cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4922 TCG_AREG0, offsetof(CPUState, psr),
4924 cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4925 TCG_AREG0, offsetof(CPUState, fsr),
4927 cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4928 TCG_AREG0, offsetof(CPUState, pc),
4930 cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4931 TCG_AREG0, offsetof(CPUState, npc),
4933 for (i = 1; i < 8; i++)
4934 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4935 offsetof(CPUState, gregs[i]),
4937 /* register helpers */
4940 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4945 void gen_pc_load(CPUState *env, TranslationBlock *tb,
4946 unsigned long searched_pc, int pc_pos, void *puc)
4949 env->pc = gen_opc_pc[pc_pos];
4950 npc = gen_opc_npc[pc_pos];
4952 /* dynamic NPC: already stored */
4953 } else if (npc == 2) {
4954 target_ulong t2 = (target_ulong)(unsigned long)puc;
4955 /* jump PC: use T2 and the jump targets of the translation */
4957 env->npc = gen_opc_jump_pc[0];
4959 env->npc = gen_opc_jump_pc[1];