extern FILE *logfile;
+static PITState *pit;
+
static void pic_irq_request(void *opaque, int level)
{
if (level) {
void cpu_mips_store_compare (CPUState *env, uint32_t value)
{
cpu_mips_update_count(env, cpu_mips_get_count(env), value);
- pic_set_irq(5, 0);
+ cpu_single_env->CP0_Cause &= ~0x00008000;
+ cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
}
static void mips_timer_cb (void *opaque)
}
#endif
cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
- pic_set_irq(5, 1);
+ cpu_single_env->CP0_Cause |= 0x00008000;
+ cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
}
void cpu_mips_clock_init (CPUState *env)
isa_mem_base = 0x10000000;
isa_pic = pic_init(pic_irq_request, cpu_single_env);
+ pit = pit_init(0x40, 0);
serial_init(0x3f8, 4, serial_hds[0]);
vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
vga_ram_size, 0, 0);