int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
{
- struct cris_mmu_result_t res;
+ struct cris_mmu_result res;
int prot, miss;
int r = -1;
target_ulong phy;
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
uint32_t phy = addr;
- struct cris_mmu_result_t res;
+ struct cris_mmu_result res;
int miss;
miss = cris_mmu_translate(&res, env, addr, 0, 0);
if (!miss)
#endif
/* rw 0 = read, 1 = write, 2 = exec. */
-static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
+static int cris_mmu_translate_page(struct cris_mmu_result *res,
CPUState *env, uint32_t vaddr,
int rw, int usermode)
{
}
}
-int cris_mmu_translate(struct cris_mmu_result_t *res,
+int cris_mmu_translate(struct cris_mmu_result *res,
CPUState *env, uint32_t vaddr,
int rw, int mmu_idx)
{
#define CRIS_MMU_ERR_WRITE 2
#define CRIS_MMU_ERR_FLUSH 3
-struct cris_mmu_result_t
+struct cris_mmu_result
{
uint32_t phy;
int prot;
void cris_mmu_init(CPUState *env);
void cris_mmu_flush_pid(CPUState *env, uint32_t pid);
-int cris_mmu_translate(struct cris_mmu_result_t *res,
+int cris_mmu_translate(struct cris_mmu_result *res,
CPUState *env, uint32_t vaddr,
int rw, int mmu_idx);