2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 static struct musb *the_musb;
116 static struct musb_ctx ctx;
118 #ifndef CONFIG_MUSB_PIO_ONLY
119 static int __initdata use_dma = 1;
121 static int __initdata use_dma;
123 module_param(use_dma, bool, 0);
124 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
126 unsigned musb_debug = 10;
127 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
128 MODULE_PARM_DESC(debug, "Debug message level. Default = 10");
130 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
131 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
133 #define MUSB_VERSION "6.0"
135 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
137 #define MUSB_DRIVER_NAME "musb_hdrc"
138 const char musb_driver_name[] = MUSB_DRIVER_NAME;
140 MODULE_DESCRIPTION(DRIVER_INFO);
141 MODULE_AUTHOR(DRIVER_AUTHOR);
142 MODULE_LICENSE("GPL");
143 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
147 inline void mbusywait(int ms)
149 unsigned long end_time = jiffies + msecs_to_jiffies(ms);
150 while(time_before(jiffies,end_time))
155 void musb_force_term(void __iomem *addr, enum musb_term term)
160 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
161 r |= ISP1704_OTG_CTRL_DP_PULLDOWN | ISP1704_OTG_CTRL_DM_PULLDOWN;
162 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
164 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
168 case MUSB_TERM_HOST_HIGHSPEED:
169 r &= ~ISP1704_FUNC_CTRL_XCVRSELECT;
170 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
171 r &= ~ISP1704_FUNC_CTRL_OPMODE;
174 case MUSB_TERM_HOST_FULLSPEED:
175 r |= 1 << ISP1704_FUNC_CTRL_XCVRSELECT_SHIFT;
176 r |= ISP1704_FUNC_CTRL_TERMSELECT;
177 r &= ~ISP1704_FUNC_CTRL_OPMODE;
180 case MUSB_TERM_HOST_LOWSPEED:
181 r |= 2 << ISP1704_FUNC_CTRL_XCVRSELECT_SHIFT;
182 r |= ISP1704_FUNC_CTRL_TERMSELECT;
183 r &= ~ISP1704_FUNC_CTRL_OPMODE;
187 ERR("Unknown musb termination\n");
191 r |= ISP1704_OTG_CTRL_IDPULLUP;
192 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
198 static inline int musb_verify_charger(void __iomem *addr)
202 /* Reset the transceiver */
203 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
204 r |= ISP1704_FUNC_CTRL_RESET;
205 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
208 /* Set normal mode */
209 r &= ~(ISP1704_FUNC_CTRL_RESET | (3 << ISP1704_FUNC_CTRL_OPMODE));
210 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
212 /* Clear the DP and DM pull-down bits */
213 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
214 r &= ~(ISP1704_OTG_CTRL_DP_PULLDOWN | ISP1704_OTG_CTRL_DM_PULLDOWN);
215 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
217 /* Enable strong pull-up on DP (1.5K) and reset */
218 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
219 r |= ISP1704_FUNC_CTRL_TERMSELECT | ISP1704_FUNC_CTRL_RESET;
220 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
223 /* Read the line state */
224 if (musb_ulpi_readb(addr, ISP1704_DEBUG)) {
225 /* Is it a charger or PS2 connection */
227 /* Enable weak pull-up resistor on DP */
228 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
229 r |= ISP1704_PWR_CTRL_DP_WKPU_EN;
230 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
232 /* Disable strong pull-up on DP (1.5K) */
233 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
234 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
235 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
237 /* Enable weak pull-down resistor on DM */
238 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
239 r |= ISP1704_OTG_CTRL_DM_PULLDOWN;
240 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
242 /* It's a charger if the line states are clear */
243 if (!(musb_ulpi_readb(addr, ISP1704_DEBUG)))
246 /* Disable weak pull-up resistor on DP */
247 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
248 r &= ~ISP1704_PWR_CTRL_DP_WKPU_EN;
249 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
253 /* Disable strong pull-up on DP (1.5K) */
254 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
255 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
256 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
262 /* Bad connections with the charger may lead into the transceiver
263 * thinking that a device was just connected. We can wait for 5 ms to
264 * ensure that these cases will generate SUSPEND interrupt and not
265 * RESET. Reading and writing to the transceiver may still cause
266 * RESET interrupts. We mask out RESET/RESUME interrupts to
269 static int check_charger;
270 static int musb_charger_detect(struct musb *musb)
272 unsigned long timeout;
277 testmode = musb_readb(musb->mregs,MUSB_TESTMODE);
281 /* Using ulpi with musb is quite tricky. The following code
282 * was written based on the ulpi application note.
284 * The order of reads and writes and quite important, don't
285 * change it unless you really know what you're doing
288 switch(musb->xceiv->state) {
289 case OTG_STATE_B_IDLE:
290 /* we always reset transceiver */
293 /* HACK: ULPI tends to get stuck when booting with
294 * the cable connected
296 r = musb_readb(musb->mregs, MUSB_DEVCTL);
297 if ((r & MUSB_DEVCTL_VBUS)
298 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
299 musb_save_ctx_and_suspend(&musb->g, 0);
300 musb_restore_ctx_and_resume(&musb->g);
301 if (musb->board && musb->board->set_pm_limits)
302 musb->board->set_pm_limits(
303 musb->controller, 1);
306 /* disable RESET and RESUME interrupts */
307 r = musb_readb(musb->mregs, MUSB_INTRUSBE);
308 r &= ~(MUSB_INTR_RESUME | MUSB_INTR_RESET);
309 musb_writeb(musb->mregs, MUSB_INTRUSBE, r);
311 if (musb->board && musb->board->xceiv_reset)
312 musb->board->xceiv_reset();
314 /* then we resume to sync with controller */
315 r = musb_readb(musb->mregs, MUSB_POWER);
316 musb_writeb(musb->mregs, MUSB_POWER,
317 r | MUSB_POWER_RESUME);
319 musb_writeb(musb->mregs, MUSB_POWER,
320 r & ~MUSB_POWER_RESUME);
322 /* now we set SW control bit in PWR_CTRL register */
323 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL,
324 ISP1704_PWR_CTRL_SWCTRL);
326 r = musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL);
327 r |= (ISP1704_PWR_CTRL_SWCTRL | ISP1704_PWR_CTRL_DPVSRC_EN);
329 /* and finally enable manual charger detection */
330 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
333 timeout = jiffies + msecs_to_jiffies(300);
334 while (!time_after(jiffies, timeout)) {
335 /* Check if there is a charger */
336 vdat = !!(musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL)
337 & ISP1704_PWR_CTRL_VDAT_DET);
342 vdat = musb_verify_charger(musb->mregs);
344 r &= ~ISP1704_PWR_CTRL_DPVSRC_EN;
346 /* Clear DPVSRC_EN, otherwise usb communication doesn't work */
347 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
355 if (vdat && !(testmode & MUSB_TEST_FORCE_HOST)) {
356 /* REVISIT: This code works only with dedicated chargers!
357 * When support for HOST/HUB chargers is added, don't
362 otg_set_suspend(musb->xceiv, 1);
363 musb->is_charger = 1;
365 /* enable interrupts */
366 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
368 /* Make sure the communication starts normally */
369 r = musb_readb(musb->mregs, MUSB_POWER);
370 musb_writeb(musb->mregs, MUSB_POWER,
371 r | MUSB_POWER_RESUME);
373 musb_writeb(musb->mregs, MUSB_POWER,
374 r & ~MUSB_POWER_RESUME);
382 /*-------------------------------------------------------------------------*/
384 static inline struct musb *dev_to_musb(struct device *dev)
386 #ifdef CONFIG_USB_MUSB_HDRC_HCD
387 /* usbcore insists dev->driver_data is a "struct hcd *" */
388 return hcd_to_musb(dev_get_drvdata(dev));
390 return dev_get_drvdata(dev);
394 /*-------------------------------------------------------------------------*/
396 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
399 * Load an endpoint's FIFO
401 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
403 void __iomem *fifo = hw_ep->fifo;
407 DBG(6, "%cX ep%d fifo %p count %d buf %p\n",
408 'T', hw_ep->epnum, fifo, len, src);
410 /* we can't assume unaligned reads work */
411 if (likely((0x01 & (unsigned long) src) == 0)) {
414 /* best case is 32bit-aligned source address */
415 if ((0x02 & (unsigned long) src) == 0) {
417 writesl(fifo, src + index, len >> 2);
418 index += len & ~0x03;
421 musb_writew(fifo, 0, *(u16 *)&src[index]);
426 writesw(fifo, src + index, len >> 1);
427 index += len & ~0x01;
431 musb_writeb(fifo, 0, src[index]);
434 writesb(fifo, src, len);
439 * Unload an endpoint's FIFO
441 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
443 void __iomem *fifo = hw_ep->fifo;
445 DBG(6, "%cX ep%d fifo %p count %d buf %p\n",
446 'R', hw_ep->epnum, fifo, len, dst);
448 /* we can't assume unaligned writes work */
449 if (likely((0x01 & (unsigned long) dst) == 0)) {
452 /* best case is 32bit-aligned destination address */
453 if ((0x02 & (unsigned long) dst) == 0) {
455 readsl(fifo, dst, len >> 2);
459 *(u16 *)&dst[index] = musb_readw(fifo, 0);
464 readsw(fifo, dst, len >> 1);
469 dst[index] = musb_readb(fifo, 0);
472 readsb(fifo, dst, len);
476 #endif /* normal PIO */
479 /*-------------------------------------------------------------------------*/
481 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
482 static const u8 musb_test_packet[53] = {
483 /* implicit SYNC then DATA0 to start */
486 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
488 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
490 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
491 /* JJJJJJJKKKKKKK x8 */
492 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
494 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
495 /* JKKKKKKK x10, JK */
496 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
498 /* implicit CRC16 then EOP to end */
501 void musb_load_testpacket(struct musb *musb)
503 void __iomem *regs = musb->endpoints[0].regs;
505 musb_ep_select(musb->mregs, 0);
506 musb_write_fifo(musb->control_ep,
507 sizeof(musb_test_packet), musb_test_packet);
508 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
511 /*-------------------------------------------------------------------------*/
513 const char *otg_state_string(struct musb *musb)
515 switch (musb->xceiv->state) {
516 case OTG_STATE_A_IDLE: return "a_idle";
517 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
518 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
519 case OTG_STATE_A_HOST: return "a_host";
520 case OTG_STATE_A_SUSPEND: return "a_suspend";
521 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
522 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
523 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
524 case OTG_STATE_B_IDLE: return "b_idle";
525 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
526 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
527 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
528 case OTG_STATE_B_HOST: return "b_host";
529 default: return "UNDEFINED";
533 #ifdef CONFIG_USB_MUSB_OTG
536 * See also USB_OTG_1-3.pdf 6.6.5 Timers
537 * REVISIT: Are the other timers done in the hardware?
539 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
542 * Handles OTG hnp timeouts, such as b_ase0_brst
544 void musb_otg_timer_func(unsigned long data)
546 struct musb *musb = (struct musb *)data;
548 spin_lock_irqsave(&musb->lock, flags);
549 switch (musb->xceiv->state) {
550 case OTG_STATE_B_WAIT_ACON:
551 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
552 musb_g_disconnect(musb);
553 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
556 case OTG_STATE_A_WAIT_BCON:
557 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
561 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
563 musb->ignore_disconnect = 0;
564 spin_unlock_irqrestore(&musb->lock, flags);
567 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
570 * Stops the B-device HNP state. Caller must take care of locking.
572 void musb_hnp_stop(struct musb *musb)
574 struct usb_hcd *hcd = musb_to_hcd(musb);
575 void __iomem *mbase = musb->mregs;
578 switch (musb->xceiv->state) {
579 case OTG_STATE_A_PERIPHERAL:
580 case OTG_STATE_A_WAIT_VFALL:
581 case OTG_STATE_A_WAIT_BCON:
582 DBG(1, "HNP: Switching back to A-host\n");
583 musb_g_disconnect(musb);
584 musb->xceiv->state = OTG_STATE_A_IDLE;
588 case OTG_STATE_B_HOST:
589 DBG(1, "HNP: Disabling HR\n");
590 hcd->self.is_b_host = 0;
591 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
593 reg = musb_readb(mbase, MUSB_POWER);
594 reg |= MUSB_POWER_SUSPENDM;
595 musb_writeb(mbase, MUSB_POWER, reg);
596 /* REVISIT: Start SESSION_REQUEST here? */
599 DBG(1, "HNP: Stopping in unknown state %s\n",
600 otg_state_string(musb));
604 * When returning to A state after HNP, avoid hub_port_rebounce(),
605 * which cause occasional OPT A "Did not receive reset after connect"
608 musb->port1_status &=
609 ~(1 << USB_PORT_FEAT_C_CONNECTION);
615 * Interrupt Service Routine to record USB "global" interrupts.
616 * Since these do not happen often and signify things of
617 * paramount importance, it seems OK to check them individually;
618 * the order of the tests is specified in the manual
620 * @param musb instance pointer
621 * @param int_usb register contents
626 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
630 irqreturn_t handled = IRQ_NONE;
631 void __iomem *mbase = musb->mregs;
634 testmode = musb_readb(mbase,MUSB_TESTMODE);
635 if(testmode & MUSB_TEST_FORCE_HOST) {
636 if(int_usb & MUSB_INTR_SESSREQ) {
637 DBG(1,"Piggybacking CONNECT on SESS REQ\n");
638 musb->int_usb |= MUSB_INTR_CONNECT;
642 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
645 /* in host mode, the peripheral may issue remote wakeup.
646 * in peripheral mode, the host may resume the link.
647 * spurious RESUME irqs happen too, paired with SUSPEND.
649 if (int_usb & MUSB_INTR_RESUME) {
650 handled = IRQ_HANDLED;
651 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
653 if (devctl & MUSB_DEVCTL_HM) {
654 #ifdef CONFIG_USB_MUSB_HDRC_HCD
655 switch (musb->xceiv->state) {
656 case OTG_STATE_A_SUSPEND:
657 /* remote wakeup? later, GetPortStatus
658 * will stop RESUME signaling
661 if (power & MUSB_POWER_SUSPENDM) {
663 musb->int_usb &= ~MUSB_INTR_SUSPEND;
664 DBG(2, "Spurious SUSPENDM\n");
668 power &= ~MUSB_POWER_SUSPENDM;
669 musb_writeb(mbase, MUSB_POWER,
670 power | MUSB_POWER_RESUME);
672 musb->port1_status |=
673 (USB_PORT_STAT_C_SUSPEND << 16)
674 | MUSB_PORT_STAT_RESUME;
675 musb->rh_timer = jiffies
676 + msecs_to_jiffies(20);
678 musb->xceiv->state = OTG_STATE_A_HOST;
680 usb_hcd_resume_root_hub(musb_to_hcd(musb));
682 case OTG_STATE_B_WAIT_ACON:
683 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
688 WARNING("bogus %s RESUME (%s)\n",
690 otg_state_string(musb));
694 switch (musb->xceiv->state) {
695 #ifdef CONFIG_USB_MUSB_HDRC_HCD
696 case OTG_STATE_A_WAIT_BCON:
697 case OTG_STATE_A_HOST:
698 case OTG_STATE_A_SUSPEND:
699 /* possibly DISCONNECT is upcoming */
700 musb->xceiv->state = OTG_STATE_A_HOST;
701 usb_hcd_resume_root_hub(musb_to_hcd(musb));
704 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
705 case OTG_STATE_B_WAIT_ACON:
706 case OTG_STATE_B_PERIPHERAL:
707 /* disconnect while suspended? we may
708 * not get a disconnect irq...
710 if ((devctl & MUSB_DEVCTL_VBUS)
711 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
713 musb->int_usb |= MUSB_INTR_DISCONNECT;
714 musb->int_usb &= ~MUSB_INTR_SUSPEND;
719 case OTG_STATE_B_IDLE:
720 musb->int_usb &= ~MUSB_INTR_SUSPEND;
724 WARNING("bogus %s RESUME (%s)\n",
726 otg_state_string(musb));
731 #ifdef CONFIG_USB_MUSB_HDRC_HCD
732 /* see manual for the order of the tests */
733 if (int_usb & MUSB_INTR_SESSREQ) {
734 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
736 /* IRQ arrives from ID pin sense or (later, if VBUS power
737 * is removed) SRP. responses are time critical:
738 * - turn on VBUS (with silicon-specific mechanism)
739 * - go through A_WAIT_VRISE
740 * - ... to A_WAIT_BCON.
741 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
742 * NOTE : Spurious SESS_REQ int's detected, which should
743 * be discarded silently.
745 if ((devctl & MUSB_DEVCTL_VBUS)
746 && host_mode(musb->mregs)) {
747 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
748 musb->ep0_stage = MUSB_EP0_START;
749 musb->xceiv->state = OTG_STATE_A_IDLE;
751 musb_set_vbus(musb, 1);
753 DBG(5,"discarding SESSREQ INT: VBUS < SessEnd\n");
756 handled = IRQ_HANDLED;
759 if (int_usb & MUSB_INTR_VBUSERROR) {
762 /* During connection as an A-Device, we may see a short
763 * current spikes causing voltage drop, because of cable
764 * and peripheral capacitance combined with vbus draw.
765 * (So: less common with truly self-powered devices, where
766 * vbus doesn't act like a power supply.)
768 * Such spikes are short; usually less than ~500 usec, max
769 * of ~2 msec. That is, they're not sustained overcurrent
770 * errors, though they're reported using VBUSERROR irqs.
772 * Workarounds: (a) hardware: use self powered devices.
773 * (b) software: ignore non-repeated VBUS errors.
775 * REVISIT: do delays from lots of DEBUG_KERNEL checks
776 * make trouble here, keeping VBUS < 4.4V ?
778 switch (musb->xceiv->state) {
779 case OTG_STATE_A_HOST:
780 /* recovery is dicey once we've gotten past the
781 * initial stages of enumeration, but if VBUS
782 * stayed ok at the other end of the link, and
783 * another reset is due (at least for high speed,
784 * to redo the chirp etc), it might work OK...
786 case OTG_STATE_A_WAIT_BCON:
787 case OTG_STATE_A_WAIT_VRISE:
788 if (musb->vbuserr_retry) {
789 musb->vbuserr_retry--;
791 devctl |= MUSB_DEVCTL_SESSION;
792 musb_writeb(mbase, MUSB_DEVCTL, devctl);
794 musb->port1_status |=
795 (1 << USB_PORT_FEAT_OVER_CURRENT)
796 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
803 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
804 otg_state_string(musb),
807 switch (devctl & MUSB_DEVCTL_VBUS) {
808 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
809 s = "<SessEnd"; break;
810 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
811 s = "<AValid"; break;
812 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
813 s = "<VBusValid"; break;
814 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
818 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
821 /* go through A_WAIT_VFALL then start a new session */
823 musb_set_vbus(musb, 0);
824 handled = IRQ_HANDLED;
827 if (int_usb & MUSB_INTR_SUSPEND) {
828 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
829 otg_state_string(musb), devctl, power);
830 handled = IRQ_HANDLED;
832 switch (musb->xceiv->state) {
833 #ifdef CONFIG_USB_MUSB_OTG
834 case OTG_STATE_A_PERIPHERAL:
836 * We cannot stop HNP here, devctl BDEVICE might be
841 case OTG_STATE_B_IDLE:
842 if (!musb->is_active)
844 case OTG_STATE_B_PERIPHERAL:
845 musb_g_suspend(musb);
846 musb->is_active = is_otg_enabled(musb)
847 && musb->xceiv->gadget->b_hnp_enable;
848 if (musb->is_active) {
849 #ifdef CONFIG_USB_MUSB_OTG
850 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
851 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
852 musb_otg_timer.data = (unsigned long)musb;
853 mod_timer(&musb_otg_timer, jiffies
854 + msecs_to_jiffies(TB_ASE0_BRST));
858 case OTG_STATE_A_WAIT_BCON:
859 if (musb->a_wait_bcon != 0)
860 musb_platform_try_idle(musb, jiffies
861 + msecs_to_jiffies(musb->a_wait_bcon));
863 case OTG_STATE_A_HOST:
864 if(testmode & MUSB_TEST_FORCE_HOST) {
865 // musb->int_usb |= MUSB_INTR_RESUME;
869 musb->xceiv->state = OTG_STATE_A_SUSPEND;
870 musb->is_active = is_otg_enabled(musb)
871 && musb->xceiv->host->b_hnp_enable;
874 case OTG_STATE_B_HOST:
875 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
876 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
879 /* "should not happen" */
885 if (int_usb & MUSB_INTR_CONNECT) {
886 struct usb_hcd *hcd = musb_to_hcd(musb);
888 handled = IRQ_HANDLED;
890 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
893 musb->ep0_stage = MUSB_EP0_START;
895 #ifdef CONFIG_USB_MUSB_OTG
896 /* flush endpoints when transitioning from Device Mode */
897 if (is_peripheral_active(musb)) {
898 /* REVISIT HNP; just force disconnect */
900 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
901 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
902 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
904 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
905 |USB_PORT_STAT_HIGH_SPEED
906 |USB_PORT_STAT_ENABLE
908 musb->port1_status |= USB_PORT_STAT_CONNECTION
909 |(USB_PORT_STAT_C_CONNECTION << 16);
911 if (testmode & MUSB_TEST_FORCE_HOST) {
913 void __iomem *mbase = musb->mregs;
915 musb_force_term(musb->mregs,MUSB_TERM_HOST_HIGHSPEED);
917 r = musb_ulpi_readb(mbase, ISP1704_DEBUG);
918 DBG(1,"Linestate %x\n",r);
921 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
922 reg = musb_readb(mbase, MUSB_TESTMODE);
923 reg &= ~MUSB_TEST_FORCE_FS;
924 reg &= ~MUSB_TEST_FORCE_HS;
925 musb_writeb(mbase, MUSB_TESTMODE, reg);
927 reg = musb_readb(mbase, MUSB_POWER);
928 reg &= ~MUSB_POWER_HSENAB;
929 musb_writeb(mbase, MUSB_POWER, reg);
931 musb_force_term(musb->mregs,MUSB_TERM_HOST_LOWSPEED);
934 /*High or full speed*/
935 reg = musb_readb(mbase, MUSB_TESTMODE);
936 if(reg & MUSB_TEST_FORCE_HS) {
938 reg &= ~MUSB_TEST_FORCE_FS;
939 musb_writeb(mbase, MUSB_TESTMODE, reg);
941 reg = musb_readb(mbase, MUSB_POWER);
942 reg |= MUSB_POWER_HSENAB;
943 musb_writeb(mbase, MUSB_POWER, reg);
946 reg |= MUSB_TEST_FORCE_FS;
947 musb_writeb(mbase, MUSB_TESTMODE, reg);
949 reg = musb_readb(mbase, MUSB_POWER);
950 reg &= ~MUSB_POWER_HSENAB;
951 musb_writeb(mbase, MUSB_POWER, reg);
954 musb_force_term(mbase,MUSB_TERM_HOST_FULLSPEED);
960 WARNING("Invalid line state of %d\n",r);
966 /* high vs full speed is just a guess until after reset */
967 if (devctl & MUSB_DEVCTL_LSDEV)
968 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
972 usb_hcd_poll_rh_status(hcd);
974 usb_hcd_resume_root_hub(hcd);
978 /* indicate new connection to OTG machine */
979 switch (musb->xceiv->state) {
980 case OTG_STATE_B_PERIPHERAL:
981 if (int_usb & MUSB_INTR_SUSPEND) {
982 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
983 musb->xceiv->state = OTG_STATE_B_HOST;
984 hcd->self.is_b_host = 1;
985 int_usb &= ~MUSB_INTR_SUSPEND;
987 DBG(1, "CONNECT as b_peripheral???\n");
989 case OTG_STATE_B_WAIT_ACON:
990 DBG(1, "HNP: Waiting to switch to b_host state\n");
991 musb->xceiv->state = OTG_STATE_B_HOST;
992 hcd->self.is_b_host = 1;
995 if ((devctl & MUSB_DEVCTL_VBUS)
996 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
997 musb->xceiv->state = OTG_STATE_A_HOST;
998 hcd->self.is_b_host = 0;
1002 DBG(1, "CONNECT (%s) devctl %02x\n",
1003 otg_state_string(musb), devctl);
1005 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1007 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
1008 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
1009 otg_state_string(musb),
1010 MUSB_MODE(musb), devctl);
1011 handled = IRQ_HANDLED;
1013 switch (musb->xceiv->state) {
1014 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1015 case OTG_STATE_A_HOST:
1016 case OTG_STATE_A_SUSPEND:
1017 usb_hcd_resume_root_hub(musb_to_hcd(musb));
1018 musb_root_disconnect(musb);
1019 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
1020 musb_platform_try_idle(musb, jiffies
1021 + msecs_to_jiffies(musb->a_wait_bcon));
1024 #ifdef CONFIG_USB_MUSB_OTG
1025 case OTG_STATE_B_HOST:
1026 musb_hnp_stop(musb);
1028 case OTG_STATE_A_PERIPHERAL:
1029 musb_hnp_stop(musb);
1030 musb_root_disconnect(musb);
1032 case OTG_STATE_B_WAIT_ACON:
1035 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1036 case OTG_STATE_B_PERIPHERAL:
1037 case OTG_STATE_B_IDLE:
1038 /* Workaround for a problem of Vbus quickly dropping
1039 * during Certification tests.
1041 * Undo the workaround on disconnect
1044 /* Disable suspend so we can write to ULPI */
1045 r = musb_readb(musb->mregs, MUSB_POWER);
1046 musb_writeb(musb->mregs, MUSB_POWER,
1047 r & ~MUSB_POWER_ENSUSPEND);
1048 musb_ulpi_writeb(musb->mregs,
1049 ISP1704_USB_INTFALL, 0x1f);
1050 musb_ulpi_writeb(musb->mregs,
1051 ISP1704_USB_INTRISE, 0x1f);
1052 musb_writeb(musb->mregs, MUSB_POWER,
1053 r | MUSB_POWER_ENSUSPEND);
1055 musb_g_disconnect(musb);
1056 /** UGLY UGLY HACK: Windows problems with multiple
1059 * This is necessary to notify gadget driver this was
1060 * a physical disconnection and not only a port reset.
1062 if (musb->gadget_driver->vbus_disconnect)
1063 musb->gadget_driver->vbus_disconnect(&musb->g);
1068 WARNING("unhandled DISCONNECT transition (%s)\n",
1069 otg_state_string(musb));
1074 /* mentor saves a bit: bus reset and babble share the same irq.
1075 * only host sees babble; only peripheral sees bus reset.
1077 if (int_usb & MUSB_INTR_RESET) {
1078 handled = IRQ_HANDLED;
1079 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
1081 * Looks like non-HS BABBLE can be ignored, but
1082 * HS BABBLE is an error condition. For HS the solution
1083 * is to avoid babble in the first place and fix what
1084 * caused BABBLE. When HS BABBLE happens we can only
1087 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
1088 DBG(1, "BABBLE devctl: %02x\n", devctl);
1090 ERR("Stopping host session -- babble\n");
1091 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1093 } else if (is_peripheral_capable()) {
1094 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
1095 switch (musb->xceiv->state) {
1096 #ifdef CONFIG_USB_OTG
1097 case OTG_STATE_A_SUSPEND:
1098 /* We need to ignore disconnect on suspend
1099 * otherwise tusb 2.0 won't reconnect after a
1100 * power cycle, which breaks otg compliance.
1102 musb->ignore_disconnect = 1;
1105 case OTG_STATE_A_HOST:
1106 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
1107 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
1108 DBG(1, "HNP: Setting timer as %s\n",
1109 otg_state_string(musb));
1110 musb_otg_timer.data = (unsigned long)musb;
1111 mod_timer(&musb_otg_timer, jiffies
1112 + msecs_to_jiffies(100));
1114 case OTG_STATE_A_PERIPHERAL:
1115 musb_hnp_stop(musb);
1117 case OTG_STATE_B_WAIT_ACON:
1118 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
1119 otg_state_string(musb));
1120 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1124 case OTG_STATE_B_IDLE:
1125 /* Workaround the charger detection problems */
1126 if ((devctl & MUSB_DEVCTL_VBUS)
1127 != (3 << MUSB_DEVCTL_VBUS_SHIFT))
1131 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1133 case OTG_STATE_B_PERIPHERAL:
1134 /* Workaround for a problem of Vbus quickly dropping
1135 * during Certification tests.
1137 * The guess is that vbus drops due to the circuitry
1138 * for overcurrent protection and that makes transceiver
1139 * think VBUS is not valid anymore. Transceiver will
1140 * then send an RXCMD to PHY which will cause it to
1141 * disconnect from the bus even though we disable the
1144 musb_ulpi_writeb(musb->mregs,
1145 ISP1704_USB_INTFALL, 0x1d);
1146 musb_ulpi_writeb(musb->mregs,
1147 ISP1704_USB_INTRISE, 0x1d);
1152 DBG(1, "Unhandled BUS RESET as %s\n",
1153 otg_state_string(musb));
1159 /* REVISIT ... this would be for multiplexing periodic endpoints, or
1160 * supporting transfer phasing to prevent exceeding ISO bandwidth
1161 * limits of a given frame or microframe.
1163 * It's not needed for peripheral side, which dedicates endpoints;
1164 * though it _might_ use SOF irqs for other purposes.
1166 * And it's not currently needed for host side, which also dedicates
1167 * endpoints, relies on TX/RX interval registers, and isn't claimed
1168 * to support ISO transfers yet.
1170 if (int_usb & MUSB_INTR_SOF) {
1171 void __iomem *mbase = musb->mregs;
1172 struct musb_hw_ep *ep;
1176 DBG(6, "START_OF_FRAME\n");
1177 handled = IRQ_HANDLED;
1179 /* start any periodic Tx transfers waiting for current frame */
1180 frame = musb_readw(mbase, MUSB_FRAME);
1181 ep = musb->endpoints;
1182 for (epnum = 1; (epnum < musb->nr_endpoints)
1183 && (musb->epmask >= (1 << epnum));
1186 * FIXME handle framecounter wraps (12 bits)
1187 * eliminate duplicated StartUrb logic
1189 if (ep->dwWaitFrame >= frame) {
1190 ep->dwWaitFrame = 0;
1191 pr_debug("SOF --> periodic TX%s on %d\n",
1192 ep->tx_channel ? " DMA" : "",
1194 if (!ep->tx_channel)
1195 musb_h_tx_start(musb, epnum);
1197 cppi_hostdma_start(musb, epnum);
1199 } /* end of for loop */
1203 schedule_work(&musb->irq_work);
1208 /*-------------------------------------------------------------------------*/
1211 * Program the HDRC to start (enable interrupts, dma, etc.).
1213 void musb_start(struct musb *musb)
1215 void __iomem *regs = musb->mregs;
1216 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1219 DBG(2, "<== devctl %02x\n", devctl);
1221 /* Ensure the clocks are on */
1222 if (musb->set_clock)
1223 musb->set_clock(musb->clock, 1);
1225 clk_enable(musb->clock);
1227 /* Set INT enable registers, enable interrupts */
1228 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
1229 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
1230 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1232 musb_writeb(regs, MUSB_TESTMODE, 0);
1234 power = MUSB_POWER_ISOUPDATE | MUSB_POWER_SOFTCONN
1235 | MUSB_POWER_HSENAB;
1237 /* ENSUSPEND wedges tusb */
1239 power |= MUSB_POWER_ENSUSPEND;
1241 /* put into basic highspeed mode and start session */
1242 musb_writeb(regs, MUSB_POWER, power);
1244 musb->is_active = 0;
1245 devctl = musb_readb(regs, MUSB_DEVCTL);
1246 devctl &= ~MUSB_DEVCTL_SESSION;
1248 if (is_otg_enabled(musb)) {
1249 /* session started after:
1250 * (a) ID-grounded irq, host mode;
1251 * (b) vbus present/connect IRQ, peripheral mode;
1252 * (c) peripheral initiates, using SRP
1254 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1255 musb->is_active = 1;
1257 devctl |= MUSB_DEVCTL_SESSION;
1259 } else if (is_host_enabled(musb)) {
1260 /* assume ID pin is hard-wired to ground */
1261 devctl |= MUSB_DEVCTL_SESSION;
1263 } else /* peripheral is enabled */ {
1264 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1265 musb->is_active = 1;
1267 musb_platform_enable(musb);
1268 musb_writeb(regs, MUSB_DEVCTL, devctl);
1272 static void musb_generic_disable(struct musb *musb)
1274 void __iomem *mbase = musb->mregs;
1277 /* Clocks need to be turned on with OFF-mode */
1278 if (musb->set_clock)
1279 musb->set_clock(musb->clock, 1);
1281 clk_enable(musb->clock);
1283 /* disable interrupts */
1284 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1285 musb_writew(mbase, MUSB_INTRTXE, 0);
1286 musb_writew(mbase, MUSB_INTRRXE, 0);
1289 musb_writeb(mbase, MUSB_DEVCTL, 0);
1291 /* flush pending interrupts */
1292 temp = musb_readb(mbase, MUSB_INTRUSB);
1293 temp = musb_readw(mbase, MUSB_INTRTX);
1294 temp = musb_readw(mbase, MUSB_INTRRX);
1298 void musb_emergency_stop(void)
1303 musb_stop(the_musb);
1305 EXPORT_SYMBOL_GPL(musb_emergency_stop);
1308 * Make the HDRC stop (disable interrupts, etc.);
1309 * reversible by musb_start
1310 * called on gadget driver unregister
1311 * with controller locked, irqs blocked
1312 * acts as a NOP unless some role activated the hardware
1314 void musb_stop(struct musb *musb)
1316 /* stop IRQs, timers, ... */
1317 musb_platform_disable(musb);
1318 musb_generic_disable(musb);
1319 DBG(3, "HDRC disabled\n");
1322 * - mark host and/or peripheral drivers unusable/inactive
1323 * - disable DMA (and enable it in HdrcStart)
1324 * - make sure we can musb_start() after musb_stop(); with
1325 * OTG mode, gadget driver module rmmod/modprobe cycles that
1328 musb_platform_try_idle(musb, 0);
1331 static void musb_shutdown(struct platform_device *pdev)
1333 struct musb *musb = dev_to_musb(&pdev->dev);
1334 unsigned long flags;
1336 spin_lock_irqsave(&musb->lock, flags);
1337 musb_platform_disable(musb);
1338 musb_generic_disable(musb);
1340 clk_put(musb->clock);
1343 spin_unlock_irqrestore(&musb->lock, flags);
1345 /* FIXME power down */
1349 /*-------------------------------------------------------------------------*/
1352 * The silicon either has hard-wired endpoint configurations, or else
1353 * "dynamic fifo" sizing. The driver has support for both, though at this
1354 * writing only the dynamic sizing is very well tested. Since we switched
1355 * away from compile-time hardware parameters, we can no longer rely on
1356 * dead code elimination to leave only the relevant one in the object file.
1358 * We don't currently use dynamic fifo setup capability to do anything
1359 * more than selecting one of a bunch of predefined configurations.
1361 #if defined(CONFIG_USB_TUSB6010) || \
1362 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
1363 static ushort __initdata fifo_mode = 4;
1365 static ushort __initdata fifo_mode = 2;
1368 /* "modprobe ... fifo_mode=1" etc */
1369 module_param(fifo_mode, ushort, 0);
1370 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1373 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1374 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1378 enum fifo_style style;
1384 * tables defining fifo_mode values. define more if you like.
1385 * for host side, make sure both halves of ep1 are set up.
1388 /* mode 0 - fits in 2KB */
1389 static struct fifo_cfg __initdata mode_0_cfg[] = {
1390 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1391 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1392 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1393 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1394 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1397 /* mode 1 - fits in 4KB */
1398 static struct fifo_cfg __initdata mode_1_cfg[] = {
1399 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1400 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1401 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1402 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1403 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1406 /* mode 2 - fits in 4KB */
1407 static struct fifo_cfg __initdata mode_2_cfg[] = {
1408 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1409 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1410 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1411 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1412 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1413 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1416 /* mode 3 - fits in 4KB */
1417 static struct fifo_cfg __initdata mode_3_cfg[] = {
1418 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1419 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1420 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1421 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1422 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1423 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1426 /* mode 4 - fits in 16KB */
1427 static struct fifo_cfg __initdata mode_4_cfg[] = {
1428 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1429 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1430 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1431 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1432 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1433 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1434 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1435 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1436 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1437 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1438 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1439 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1440 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1441 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1442 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1443 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 64, },
1444 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1445 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 64, },
1446 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1447 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1448 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1449 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 256, },
1450 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1451 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 256, },
1452 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 256, },
1453 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 4096, },
1454 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1455 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1458 /* mode 5 - fits in 16KB */
1459 static struct fifo_cfg __initdata mode_5_cfg[] = {
1460 /* phonet or mass storage */
1461 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1462 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1465 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1466 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1469 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1470 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1473 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1474 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1475 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 16, },
1478 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1479 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1480 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 16, },
1483 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1484 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1486 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1487 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1489 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1490 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1492 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1493 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1497 * configure a fifo; for non-shared endpoints, this may be called
1498 * once for a tx fifo and once for an rx fifo.
1500 * returns negative errno or offset for next fifo.
1503 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1504 const struct fifo_cfg *cfg, u16 offset)
1506 void __iomem *mbase = musb->mregs;
1508 u16 maxpacket = cfg->maxpacket;
1509 u16 c_off = offset >> 3;
1512 /* expect hw_ep has already been zero-initialized */
1514 size = ffs(max(maxpacket, (u16) 8)) - 1;
1515 maxpacket = 1 << size;
1518 if (cfg->mode == BUF_DOUBLE) {
1519 if ((offset + (maxpacket << 1)) >
1520 (1 << (musb->config->ram_bits + 2)))
1522 c_size |= MUSB_FIFOSZ_DPB;
1524 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1528 /* configure the FIFO */
1529 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1531 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1532 /* EP0 reserved endpoint for control, bidirectional;
1533 * EP1 reserved for bulk, two unidirection halves.
1535 if (hw_ep->epnum == 1)
1536 musb->bulk_ep = hw_ep;
1537 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1539 switch (cfg->style) {
1541 musb_write_txfifosz(mbase, c_size);
1542 musb_write_txfifoadd(mbase, c_off);
1543 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1544 hw_ep->max_packet_sz_tx = maxpacket;
1545 ctx.txfifosz[hw_ep->epnum] = c_size;
1546 ctx.txfifoadd[hw_ep->epnum] = c_off;
1549 musb_write_rxfifosz(mbase, c_size);
1550 musb_write_rxfifoadd(mbase, c_off);
1551 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1552 hw_ep->max_packet_sz_rx = maxpacket;
1553 ctx.rxfifosz[hw_ep->epnum] = c_size;
1554 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1557 musb_write_txfifosz(mbase, c_size);
1558 musb_write_txfifoadd(mbase, c_off);
1559 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1560 hw_ep->max_packet_sz_rx = maxpacket;
1562 musb_write_rxfifosz(mbase, c_size);
1563 musb_write_rxfifoadd(mbase, c_off);
1564 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1565 hw_ep->max_packet_sz_tx = maxpacket;
1567 /* Save the context of endpoints. */
1568 ctx.rxfifosz[hw_ep->epnum] = c_size;
1569 ctx.txfifosz[hw_ep->epnum] = c_size;
1570 ctx.txfifoadd[hw_ep->epnum] = c_off;
1571 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1573 hw_ep->is_shared_fifo = true;
1577 /* NOTE rx and tx endpoint irqs aren't managed separately,
1578 * which happens to be ok
1580 musb->epmask |= (1 << hw_ep->epnum);
1582 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1585 static struct fifo_cfg __initdata ep0_cfg = {
1586 .style = FIFO_RXTX, .maxpacket = 64,
1589 static int __init ep_config_from_table(struct musb *musb)
1591 const struct fifo_cfg *cfg;
1594 struct musb_hw_ep *hw_ep = musb->endpoints;
1596 if (machine_is_nokia_rx51())
1599 switch (fifo_mode) {
1605 n = ARRAY_SIZE(mode_0_cfg);
1609 n = ARRAY_SIZE(mode_1_cfg);
1613 n = ARRAY_SIZE(mode_2_cfg);
1617 n = ARRAY_SIZE(mode_3_cfg);
1621 n = ARRAY_SIZE(mode_4_cfg);
1625 n = ARRAY_SIZE(mode_5_cfg);
1629 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1630 musb_driver_name, fifo_mode);
1633 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1634 /* assert(offset > 0) */
1636 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1637 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1640 for (i = 0; i < n; i++) {
1641 u8 epn = cfg->hw_ep_num;
1643 if (epn >= musb->config->num_eps) {
1644 pr_debug("%s: invalid ep %d\n",
1645 musb_driver_name, epn);
1648 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1650 pr_debug("%s: mem overrun, ep %d\n",
1651 musb_driver_name, epn);
1655 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1658 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1660 n + 1, musb->config->num_eps * 2 - 1,
1661 offset, (1 << (musb->config->ram_bits + 2)));
1663 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1664 if (!musb->bulk_ep) {
1665 pr_debug("%s: missing bulk\n", musb_driver_name);
1675 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1676 * @param musb the controller
1678 static int __init ep_config_from_hw(struct musb *musb)
1681 struct musb_hw_ep *hw_ep;
1682 void *mbase = musb->mregs;
1685 DBG(2, "<== static silicon ep config\n");
1687 /* FIXME pick up ep0 maxpacket size */
1689 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1690 musb_ep_select(mbase, epnum);
1691 hw_ep = musb->endpoints + epnum;
1693 ret = musb_read_fifosize(musb, hw_ep, epnum);
1697 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1699 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1700 /* pick an RX/TX endpoint for bulk */
1701 if (hw_ep->max_packet_sz_tx < 512
1702 || hw_ep->max_packet_sz_rx < 512)
1705 /* REVISIT: this algorithm is lazy, we should at least
1706 * try to pick a double buffered endpoint.
1710 musb->bulk_ep = hw_ep;
1714 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1715 if (!musb->bulk_ep) {
1716 pr_debug("%s: missing bulk\n", musb_driver_name);
1724 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1726 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1727 * configure endpoints, or take their config from silicon
1729 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1736 u16 hwvers, rev_major, rev_minor;
1737 char aInfo[78], aRevision[32], aDate[12];
1738 void __iomem *mbase = musb->mregs;
1742 /* log core options (read using indexed model) */
1743 musb_ep_select(mbase, 0);
1744 reg = musb_read_configdata(mbase);
1746 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1747 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1748 strcat(aInfo, ", dyn FIFOs");
1749 if (reg & MUSB_CONFIGDATA_MPRXE) {
1750 strcat(aInfo, ", bulk combine");
1752 musb->bulk_combine = true;
1754 strcat(aInfo, " (X)"); /* no driver support */
1757 if (reg & MUSB_CONFIGDATA_MPTXE) {
1758 strcat(aInfo, ", bulk split");
1760 musb->bulk_split = true;
1762 strcat(aInfo, " (X)"); /* no driver support */
1765 if (reg & MUSB_CONFIGDATA_HBRXE) {
1766 strcat(aInfo, ", HB-ISO Rx");
1767 strcat(aInfo, " (X)"); /* no driver support */
1769 if (reg & MUSB_CONFIGDATA_HBTXE) {
1770 strcat(aInfo, ", HB-ISO Tx");
1771 strcat(aInfo, " (X)"); /* no driver support */
1773 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1774 strcat(aInfo, ", SoftConn");
1776 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1777 musb_driver_name, reg, aInfo);
1780 data = musb_readl(mbase, 0x404);
1781 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1782 (data >> 16) & 0xff, (data >> 24) & 0xff);
1783 /* FIXME ID2 and ID3 are unused */
1784 data = musb_readl(mbase, 0x408);
1785 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1786 data = musb_readl(mbase, 0x40c);
1787 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1788 reg = musb_readb(mbase, 0x400);
1789 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1793 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1794 musb->is_multipoint = 1;
1797 musb->is_multipoint = 0;
1799 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1800 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1802 "%s: kernel must blacklist external hubs\n",
1808 /* log release info */
1809 hwvers = musb_read_hwvers(mbase);
1810 rev_major = (hwvers >> 10) & 0x1f;
1811 rev_minor = hwvers & 0x3ff;
1812 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1813 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1814 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1815 musb_driver_name, type, aRevision, aDate);
1818 musb_configure_ep0(musb);
1820 /* discover endpoint configuration */
1821 musb->nr_endpoints = 1;
1824 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1825 if (musb->config->dyn_fifo)
1826 status = ep_config_from_table(musb);
1828 ERR("reconfigure software for Dynamic FIFOs\n");
1832 if (!musb->config->dyn_fifo)
1833 status = ep_config_from_hw(musb);
1835 ERR("reconfigure software for static FIFOs\n");
1843 /* finish init, and print endpoint config */
1844 for (i = 0; i < musb->nr_endpoints; i++) {
1845 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1847 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1848 #ifdef CONFIG_USB_TUSB6010
1849 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1850 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1851 hw_ep->fifo_sync_va =
1852 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1855 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1857 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1860 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1861 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1862 /* init list of in and out qhs */
1863 INIT_LIST_HEAD(&hw_ep->in_list);
1864 INIT_LIST_HEAD(&hw_ep->out_list);
1865 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1866 hw_ep->rx_reinit = 1;
1867 hw_ep->tx_reinit = 1;
1870 if (hw_ep->max_packet_sz_tx) {
1872 "%s: hw_ep %d%s, %smax %d\n",
1873 musb_driver_name, i,
1874 hw_ep->is_shared_fifo ? "shared" : "tx",
1875 hw_ep->tx_double_buffered
1876 ? "doublebuffer, " : "",
1877 hw_ep->max_packet_sz_tx);
1879 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1881 "%s: hw_ep %d%s, %smax %d\n",
1882 musb_driver_name, i,
1884 hw_ep->rx_double_buffered
1885 ? "doublebuffer, " : "",
1886 hw_ep->max_packet_sz_rx);
1888 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1889 DBG(1, "hw_ep %d not configured\n", i);
1895 /*-------------------------------------------------------------------------*/
1897 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1899 static irqreturn_t generic_interrupt(int irq, void *__hci)
1901 unsigned long flags;
1902 irqreturn_t retval = IRQ_NONE;
1903 struct musb *musb = __hci;
1905 spin_lock_irqsave(&musb->lock, flags);
1907 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1908 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1909 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1911 while (musb->int_usb || musb->int_tx || musb->int_rx)
1912 retval |= musb_interrupt(musb);
1914 spin_unlock_irqrestore(&musb->lock, flags);
1916 /* REVISIT we sometimes get spurious IRQs on g_ep0
1919 if (retval != IRQ_HANDLED)
1920 DBG(5, "spurious?\n");
1926 #define generic_interrupt NULL
1930 * handle all the irqs defined by the HDRC core. for now we expect: other
1931 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1932 * will be assigned, and the irq will already have been acked.
1934 * called in irq context with spinlock held, irqs blocked
1936 irqreturn_t musb_interrupt(struct musb *musb)
1938 irqreturn_t retval = IRQ_NONE;
1939 u8 devctl, power, int_usb;
1943 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1944 power = musb_readb(musb->mregs, MUSB_POWER);
1946 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1947 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1948 musb->int_usb, musb->int_tx, musb->int_rx);
1950 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1951 if (is_otg_enabled(musb)|| is_peripheral_enabled(musb))
1952 if (!musb->gadget_driver) {
1953 DBG(5, "No gadget driver loaded\n");
1961 /* the core can interrupt us for multiple reasons; docs have
1962 * a generic interrupt flowchart to follow
1964 int_usb = musb->int_usb;
1966 int_usb &= ~MUSB_INTR_SOF;
1968 retval |= musb_stage0_irq(musb, int_usb, devctl, power);
1970 /* "stage 1" is handling endpoint irqs */
1972 /* handle endpoint 0 first */
1973 if (musb->int_tx & 1) {
1975 if (devctl & MUSB_DEVCTL_HM)
1976 retval |= musb_h_ep0_irq(musb);
1978 retval |= musb_g_ep0_irq(musb);
1981 /* TX on endpoints 1-15 */
1982 reg = musb->int_tx >> 1;
1987 /* musb_ep_select(musb->mregs, ep_num); */
1988 /* REVISIT just retval |= ep->tx_irq(...) */
1989 retval = IRQ_HANDLED;
1990 if (devctl & MUSB_DEVCTL_HM) {
1991 if (is_host_capable())
1992 musb_host_tx(musb, ep_num);
1994 if (is_peripheral_capable())
1995 musb_g_tx(musb, ep_num);
2002 /* RX on endpoints 1-15 */
2003 reg = musb->int_rx >> 1;
2008 /* musb_ep_select(musb->mregs, ep_num); */
2009 /* REVISIT just retval = ep->rx_irq(...) */
2010 retval = IRQ_HANDLED;
2011 if (devctl & MUSB_DEVCTL_HM) {
2012 if (is_host_capable())
2013 musb_host_rx(musb, ep_num);
2015 if (is_peripheral_capable())
2016 musb_g_rx(musb, ep_num, false);
2028 #ifndef CONFIG_MUSB_PIO_ONLY
2029 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
2031 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2033 /* called with controller lock already held */
2036 #ifndef CONFIG_USB_TUSB_OMAP_DMA
2037 if (!cppi_ti_dma()) {
2039 if (devctl & MUSB_DEVCTL_HM)
2040 musb_h_ep0_irq(musb);
2042 musb_g_ep0_irq(musb);
2046 /* endpoints 1..15 */
2048 if (devctl & MUSB_DEVCTL_HM) {
2049 if (is_host_capable())
2050 musb_host_tx(musb, epnum);
2052 if (is_peripheral_capable())
2053 musb_g_tx(musb, epnum);
2057 if (devctl & MUSB_DEVCTL_HM) {
2058 if (is_host_capable())
2059 musb_host_rx(musb, epnum);
2061 if (is_peripheral_capable())
2062 musb_g_rx(musb, epnum, true);
2069 /*-------------------------------------------------------------------------*/
2074 musb_charger_show(struct device *dev, struct device_attribute *attr, char *buf)
2076 struct musb *musb = dev_to_musb(dev);
2078 return sprintf(buf, "%d\n", (musb->is_charger ?
2079 musb->is_charger : musb_charger_detect(musb)));
2081 static DEVICE_ATTR(charger, 0444, musb_charger_show, NULL);
2084 musb_amp_show(struct device *dev, struct device_attribute *attr, char *buf)
2086 struct musb *musb = dev_to_musb(dev);
2088 return sprintf(buf, "%d\n", musb->power_draw);
2090 static DEVICE_ATTR(mA, 0444, musb_amp_show, NULL);
2093 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
2095 struct musb *musb = dev_to_musb(dev);
2098 mutex_lock(&musb->mutex);
2099 ret = sprintf(buf, "%s\n", otg_state_string(musb));
2100 mutex_unlock(&musb->mutex);
2106 musb_connect_show(struct device *dev, struct device_attribute *attr, char *buf)
2108 struct musb *musb = dev_to_musb(dev);
2109 unsigned long flags;
2112 spin_lock_irqsave(&musb->lock, flags);
2113 ret = sprintf(buf, "%d\n", musb->softconnect);
2114 spin_unlock_irqrestore(&musb->lock, flags);
2120 musb_connect_store(struct device *dev, struct device_attribute *attr,
2121 const char *buf, size_t n)
2123 struct musb *musb = dev_to_musb(dev);
2124 unsigned long flags;
2129 status = sscanf(buf, "%u", &val);
2131 printk(KERN_ERR "invalid parameter, %d\n", status);
2135 spin_lock_irqsave(&musb->lock, flags);
2137 power = musb_readb(musb->mregs, MUSB_POWER);
2140 power |= MUSB_POWER_SOFTCONN;
2142 power &= ~MUSB_POWER_SOFTCONN;
2144 musb->softconnect = !!val;
2145 musb_writeb(musb->mregs, MUSB_POWER, power);
2147 spin_unlock_irqrestore(&musb->lock, flags);
2151 static DEVICE_ATTR(connect, 0644, musb_connect_show, musb_connect_store);
2154 musb_mode_store(struct device *dev, struct device_attribute *attr,
2155 const char *buf, size_t n)
2157 struct musb *musb = dev_to_musb(dev);
2160 mutex_lock(&musb->mutex);
2161 if (sysfs_streq(buf, "host"))
2162 status = musb_platform_set_mode(musb, MUSB_HOST);
2163 else if (sysfs_streq(buf, "peripheral"))
2164 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2165 else if (sysfs_streq(buf, "otg"))
2166 status = musb_platform_set_mode(musb, MUSB_OTG);
2169 mutex_unlock(&musb->mutex);
2171 return (status == 0) ? n : status;
2173 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
2176 musb_vbus_store(struct device *dev, struct device_attribute *attr,
2177 const char *buf, size_t n)
2179 struct musb *musb = dev_to_musb(dev);
2180 unsigned long flags;
2183 if (sscanf(buf, "%lu", &val) < 1) {
2184 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
2188 spin_lock_irqsave(&musb->lock, flags);
2189 musb->a_wait_bcon = val;
2190 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
2191 musb->is_active = 0;
2192 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
2193 spin_unlock_irqrestore(&musb->lock, flags);
2199 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
2201 struct musb *musb = dev_to_musb(dev);
2202 unsigned long flags;
2206 spin_lock_irqsave(&musb->lock, flags);
2207 val = musb->a_wait_bcon;
2208 vbus = musb_platform_get_vbus_status(musb);
2209 spin_unlock_irqrestore(&musb->lock, flags);
2211 return sprintf(buf, "Vbus %s, timeout %lu\n",
2212 vbus ? "on" : "off", val);
2214 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
2216 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2219 musb_suspend_show(struct device *dev, struct device_attribute *attr, char *buf)
2221 struct musb *musb = dev_to_musb(dev);
2223 return sprintf(buf, "%d\n", musb->is_suspended);
2225 static DEVICE_ATTR(suspend, 0444, musb_suspend_show, NULL);
2227 /* Gadget drivers can't know that a host is connected so they might want
2228 * to start SRP, but users can. This allows userspace to trigger SRP.
2231 musb_srp_store(struct device *dev, struct device_attribute *attr,
2232 const char *buf, size_t n)
2234 struct musb *musb = dev_to_musb(dev);
2237 if (sscanf(buf, "%hu", &srp) != 1
2239 printk(KERN_ERR "SRP: Value must be 1\n");
2244 musb_g_wakeup(musb);
2248 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
2250 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2254 /* Only used to provide driver mode change events */
2255 static void musb_irq_work(struct work_struct *data)
2257 struct musb *musb = container_of(data, struct musb, irq_work);
2258 static int old_state, old_ma, old_suspend;
2260 if (musb->xceiv->state != old_state) {
2261 old_state = musb->xceiv->state;
2262 sysfs_notify(&musb->controller->kobj, NULL, "mode");
2264 if (musb->power_draw != old_ma) {
2265 old_ma = musb->power_draw;
2266 sysfs_notify(&musb->controller->kobj, NULL, "mA");
2268 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2269 if (old_suspend != musb->is_suspended) {
2270 old_suspend = musb->is_suspended;
2271 sysfs_notify(&musb->controller->kobj, NULL, "suspend");
2276 /* --------------------------------------------------------------------------
2280 static struct musb *__init
2281 allocate_instance(struct device *dev,
2282 struct musb_hdrc_config *config, void __iomem *mbase)
2285 struct musb_hw_ep *ep;
2287 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2288 struct usb_hcd *hcd;
2290 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2293 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2295 musb = hcd_to_musb(hcd);
2297 hcd->uses_new_polling = 1;
2299 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2301 musb = kzalloc(sizeof *musb, GFP_KERNEL);
2304 dev_set_drvdata(dev, musb);
2308 musb->mregs = mbase;
2309 musb->ctrl_base = mbase;
2310 musb->nIrq = -ENODEV;
2311 musb->config = config;
2312 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2313 for (epnum = 0, ep = musb->endpoints;
2314 epnum < musb->config->num_eps;
2320 musb->controller = dev;
2324 static void musb_free(struct musb *musb)
2326 /* this has multiple entry modes. it handles fault cleanup after
2327 * probe(), where things may be partially set up, as well as rmmod
2328 * cleanup after everything's been de-activated.
2332 device_remove_file(musb->controller, &dev_attr_mA);
2333 device_remove_file(musb->controller, &dev_attr_connect);
2334 device_remove_file(musb->controller, &dev_attr_charger);
2335 device_remove_file(musb->controller, &dev_attr_mode);
2336 device_remove_file(musb->controller, &dev_attr_vbus);
2337 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2338 device_remove_file(musb->controller, &dev_attr_suspend);
2339 device_remove_file(musb->controller, &dev_attr_srp);
2343 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2344 musb_gadget_cleanup(musb);
2347 if (musb->nIrq >= 0) {
2349 disable_irq_wake(musb->nIrq);
2350 free_irq(musb->nIrq, musb);
2352 if (is_dma_capable() && musb->dma_controller) {
2353 struct dma_controller *c = musb->dma_controller;
2356 dma_controller_destroy(c);
2359 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2360 musb_platform_exit(musb);
2361 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2364 clk_disable(musb->clock);
2365 clk_put(musb->clock);
2368 #ifdef CONFIG_USB_MUSB_OTG
2369 put_device(musb->xceiv->dev);
2372 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2373 usb_put_hcd(musb_to_hcd(musb));
2380 * Perform generic per-controller initialization.
2382 * @pDevice: the controller (already clocked, etc)
2384 * @mregs: virtual address of controller registers,
2385 * not yet corrected for platform-specific offsets
2388 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2392 struct musb_hdrc_platform_data *plat = dev->platform_data;
2394 /* The driver might handle more features than the board; OK.
2395 * Fail when the board needs a feature that's not enabled.
2398 dev_dbg(dev, "no platform_data?\n");
2401 switch (plat->mode) {
2403 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2408 case MUSB_PERIPHERAL:
2409 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2415 #ifdef CONFIG_USB_MUSB_OTG
2421 dev_err(dev, "incompatible Kconfig role setting\n");
2426 musb = allocate_instance(dev, plat->config, ctrl);
2432 spin_lock_init(&musb->lock);
2433 mutex_init(&musb->mutex);
2434 musb->board = plat->board;
2435 musb->board_mode = plat->mode;
2436 musb->board_set_power = plat->set_power;
2437 musb->set_clock = plat->set_clock;
2438 musb->min_power = plat->min_power;
2439 musb->use_dma = use_dma;
2441 /* Clock usage is chip-specific ... functional clock (DaVinci,
2442 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
2443 * code does is make sure a clock handle is available; platform
2444 * code manages it during start/stop and suspend/resume.
2447 musb->clock = clk_get(dev, plat->clock);
2448 if (IS_ERR(musb->clock)) {
2449 status = PTR_ERR(musb->clock);
2455 /* assume vbus is off */
2457 /* platform adjusts musb->mregs and musb->isr if needed,
2458 * and activates clocks
2460 musb->isr = generic_interrupt;
2461 status = musb_platform_init(musb);
2470 #ifndef CONFIG_MUSB_PIO_ONLY
2471 if (use_dma && dev->dma_mask) {
2472 struct dma_controller *c;
2474 c = dma_controller_create(musb, musb->mregs);
2475 musb->dma_controller = c;
2480 /* ideally this would be abstracted in platform setup */
2481 if (!musb->use_dma || !musb->dma_controller)
2482 dev->dma_mask = NULL;
2484 /* be sure interrupts are disabled before connecting ISR */
2485 musb_platform_disable(musb);
2486 musb_generic_disable(musb);
2488 /* setup musb parts of the core (especially endpoints) */
2489 status = musb_core_init(plat->config->multipoint
2490 ? MUSB_CONTROLLER_MHDRC
2491 : MUSB_CONTROLLER_HDRC, musb);
2495 /* Init IRQ workqueue before request_irq */
2496 INIT_WORK(&musb->irq_work, musb_irq_work);
2498 /* attach to the IRQ */
2499 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2500 dev_err(dev, "request_irq %d failed!\n", nIrq);
2505 /* FIXME this handles wakeup irqs wrong */
2506 if (enable_irq_wake(nIrq) == 0) {
2508 device_init_wakeup(dev, 1);
2513 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2516 switch (musb->board_mode) {
2517 case MUSB_HOST: s = "Host"; break;
2518 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2519 default: s = "OTG"; break;
2522 (is_dma_capable() && musb->dma_controller)
2526 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2527 /* host side needs more setup, except for no-host modes */
2528 if (musb->board_mode != MUSB_PERIPHERAL) {
2529 struct usb_hcd *hcd = musb_to_hcd(musb);
2531 if (musb->board_mode == MUSB_OTG)
2532 hcd->self.otg_port = 1;
2533 musb->xceiv->host = &hcd->self;
2534 hcd->power_budget = 2 * (plat->power ? : 250);
2536 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2538 /* For the host-only role, we can activate right away.
2539 * (We expect the ID pin to be forcibly grounded!!)
2540 * Otherwise, wait till the gadget driver hooks up.
2542 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2543 MUSB_HST_MODE(musb);
2544 musb->xceiv->default_a = 1;
2545 musb->xceiv->state = OTG_STATE_A_IDLE;
2547 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2551 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2553 musb_readb(musb->mregs, MUSB_DEVCTL),
2554 (!host_mode(musb->mregs)
2557 } else /* peripheral is enabled */ {
2558 MUSB_DEV_MODE(musb);
2559 musb->xceiv->default_a = 0;
2560 musb->xceiv->state = OTG_STATE_B_IDLE;
2562 status = musb_gadget_setup(musb);
2566 DBG(1, "%s mode, status %d, dev%02x\n",
2567 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2569 musb_readb(musb->mregs, MUSB_DEVCTL));
2573 if (!(musb_debug_create("driver/musb_hdrc", musb)))
2574 DBG(1, "could not create procfs entry\n");
2577 status = device_create_file(dev, &dev_attr_mA);
2578 status = device_create_file(dev, &dev_attr_connect);
2579 status = device_create_file(dev, &dev_attr_charger);
2580 status = device_create_file(dev, &dev_attr_mode);
2581 status = device_create_file(dev, &dev_attr_vbus);
2582 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2583 status = device_create_file(dev, &dev_attr_suspend);
2584 status = device_create_file(dev, &dev_attr_srp);
2585 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2591 /* Resets the controller. Has to be done. Without this, most likely
2592 * the state machine inside the transceiver doesn't get fixed properly
2594 musb_save_ctx_and_suspend(&musb->g, 0);
2595 musb_restore_ctx_and_resume(&musb->g);
2601 device_remove_file(dev, &dev_attr_mA);
2602 device_remove_file(dev, &dev_attr_connect);
2603 device_remove_file(dev, &dev_attr_charger);
2604 device_remove_file(musb->controller, &dev_attr_mode);
2605 device_remove_file(musb->controller, &dev_attr_vbus);
2606 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2607 device_remove_file(musb->controller, &dev_attr_suspend);
2608 device_remove_file(musb->controller, &dev_attr_srp);
2611 musb_platform_exit(musb);
2613 dev_err(musb->controller,
2614 "musb_init_controller failed with status %d\n", status);
2617 clk_put(musb->clock);
2618 device_init_wakeup(dev, 0);
2625 /*-------------------------------------------------------------------------*/
2627 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2628 * bridge to a platform device; this driver then suffices.
2631 #ifndef CONFIG_MUSB_PIO_ONLY
2632 static u64 *orig_dma_mask;
2635 static int __init musb_probe(struct platform_device *pdev)
2637 struct device *dev = &pdev->dev;
2638 int irq = platform_get_irq(pdev, 0);
2639 struct resource *iomem;
2642 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2643 if (!iomem || irq == 0)
2646 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2648 dev_err(dev, "ioremap failed\n");
2652 #ifndef CONFIG_MUSB_PIO_ONLY
2653 /* clobbered by use_dma=n */
2654 orig_dma_mask = dev->dma_mask;
2656 /* Store initial mask for USB interrupts */
2657 ctx.intrusbe = 0xf7;
2659 return musb_init_controller(dev, irq, base);
2662 static int __devexit musb_remove(struct platform_device *pdev)
2664 struct musb *musb = dev_to_musb(&pdev->dev);
2665 void __iomem *ctrl_base = musb->ctrl_base;
2667 /* this gets called on rmmod.
2668 * - Host mode: host may still be active
2669 * - Peripheral mode: peripheral is deactivated (or never-activated)
2670 * - OTG mode: both roles are deactivated (or never-activated)
2672 musb_shutdown(pdev);
2673 musb_debug_delete("driver/musb_hdrc", musb);
2674 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2675 if (musb->board_mode == MUSB_HOST)
2676 usb_remove_hcd(musb_to_hcd(musb));
2680 device_init_wakeup(&pdev->dev, 0);
2681 #ifndef CONFIG_MUSB_PIO_ONLY
2682 pdev->dev.dma_mask = orig_dma_mask;
2689 void musb_save_ctx(struct musb *musb)
2691 ctx.power = musb_readb(musb->mregs, MUSB_POWER);
2692 ctx.intrtxe = musb_readw(musb->mregs, MUSB_INTRTXE);
2693 ctx.intrrxe = musb_readw(musb->mregs, MUSB_INTRRXE);
2694 ctx.intrusbe = musb_readb(musb->mregs, MUSB_INTRUSBE);
2695 ctx.devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2698 void musb_restore_ctx(struct musb *musb)
2701 musb_writeb(musb->mregs, MUSB_POWER, ctx.power);
2702 musb_writew(musb->mregs, MUSB_INTRTX, 0x00);
2703 musb_writew(musb->mregs, MUSB_INTRTXE, ctx.intrtxe);
2704 musb_writew(musb->mregs, MUSB_INTRRX, 0x00);
2705 musb_writew(musb->mregs, MUSB_INTRRXE, ctx.intrrxe);
2706 musb_writeb(musb->mregs, MUSB_INTRUSB, 0x00);
2707 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
2708 musb_writeb(musb->mregs, MUSB_DEVCTL, ctx.devctl);
2710 /* iterate over every endpoint, select it and restore its context */
2711 for (i = 0; i < musb->config->num_eps; i++) {
2712 musb_writeb(musb->mregs, MUSB_INDEX, i);
2713 musb_writeb(musb->mregs, MUSB_RXFIFOSZ, ctx.rxfifosz[i]);
2714 musb_writeb(musb->mregs, MUSB_TXFIFOSZ, ctx.txfifosz[i]);
2715 musb_writew(musb->mregs, MUSB_TXFIFOADD, ctx.txfifoadd[i]);
2716 musb_writew(musb->mregs, MUSB_RXFIFOADD, ctx.rxfifoadd[i]);
2720 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2722 unsigned long flags;
2723 struct musb *musb = dev_to_musb(&pdev->dev);
2728 spin_lock_irqsave(&musb->lock, flags);
2730 if (is_peripheral_active(musb)) {
2731 /* FIXME force disconnect unless we know USB will wake
2732 * the system up quickly enough to respond ...
2734 } else if (is_host_active(musb)) {
2735 /* we know all the children are suspended; sometimes
2736 * they will even be wakeup-enabled.
2741 musb_save_ctx(musb);
2743 if (musb->set_clock)
2744 musb->set_clock(musb->clock, 0);
2746 clk_disable(musb->clock);
2748 spin_unlock_irqrestore(&musb->lock, flags);
2752 static int musb_resume(struct platform_device *pdev)
2754 unsigned long flags;
2755 struct musb *musb = dev_to_musb(&pdev->dev);
2760 spin_lock_irqsave(&musb->lock, flags);
2762 if (musb->set_clock)
2763 musb->set_clock(musb->clock, 1);
2765 clk_enable(musb->clock);
2767 /* restore context */
2768 musb_restore_ctx(musb);
2770 /* for static cmos like DaVinci, register values were preserved
2771 * unless for some reason the whole soc powered down and we're
2772 * not treating that as a whole-system restart (e.g. swsusp)
2774 spin_unlock_irqrestore(&musb->lock, flags);
2779 #define musb_suspend NULL
2780 #define musb_resume NULL
2783 static struct platform_driver musb_driver = {
2785 .name = (char *)musb_driver_name,
2786 .bus = &platform_bus_type,
2787 .owner = THIS_MODULE,
2789 .remove = __devexit_p(musb_remove),
2790 .shutdown = musb_shutdown,
2791 .suspend = musb_suspend,
2792 .resume = musb_resume,
2795 /*-------------------------------------------------------------------------*/
2797 static int __init musb_init(void)
2799 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2804 pr_info("%s: version " MUSB_VERSION ", "
2805 #ifdef CONFIG_MUSB_PIO_ONLY
2807 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2809 #elif defined(CONFIG_USB_INVENTRA_DMA)
2811 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2817 #ifdef CONFIG_USB_MUSB_OTG
2818 "otg (peripheral+host)"
2819 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2821 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2825 musb_driver_name, musb_debug);
2826 return platform_driver_probe(&musb_driver, musb_probe);
2829 /* make us init after usbcore and before usb
2830 * gadget and host-side drivers start to register
2832 subsys_initcall(musb_init);
2834 static void __exit musb_cleanup(void)
2836 platform_driver_unregister(&musb_driver);
2838 module_exit(musb_cleanup);