2 * QEMU ETRAX System Emulator
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu-char.h"
33 #define RW_TR_CTRL (0x00 / 4)
34 #define RW_TR_DMA_EN (0x04 / 4)
35 #define RW_REC_CTRL (0x08 / 4)
36 #define RW_DOUT (0x1c / 4)
37 #define RS_STAT_DIN (0x20 / 4)
38 #define R_STAT_DIN (0x24 / 4)
39 #define RW_INTR_MASK (0x2c / 4)
40 #define RW_ACK_INTR (0x30 / 4)
41 #define R_INTR (0x34 / 4)
42 #define R_MASKED_INTR (0x38 / 4)
43 #define R_MAX (0x3c / 4)
46 #define STAT_TR_IDLE 22
47 #define STAT_TR_RDY 24
55 /* This pending thing is a hack. */
58 /* Control registers. */
62 static void ser_update_irq(struct etrax_serial *s)
64 s->regs[R_INTR] &= ~(s->regs[RW_ACK_INTR]);
65 s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
67 qemu_set_irq(s->irq[0], !!s->regs[R_MASKED_INTR]);
68 s->regs[RW_ACK_INTR] = 0;
71 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
73 struct etrax_serial *s = opaque;
74 D(CPUState *env = s->env);
81 r = s->regs[RS_STAT_DIN];
85 /* Read side-effect: clear dav. */
86 s->regs[addr] &= ~(1 << STAT_DAV);
90 D(printf ("%s %x=%x\n", __func__, addr, r));
97 ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
99 struct etrax_serial *s = opaque;
100 unsigned char ch = value;
101 D(CPUState *env = s->env);
103 D(printf ("%s %x %x\n", __func__, addr, value));
108 qemu_chr_write(s->chr, &ch, 1);
109 s->regs[R_INTR] |= 1;
111 s->regs[addr] = value;
114 s->regs[addr] = value;
115 if (s->pending_tx && (s->regs[addr] & 1)) {
116 s->regs[R_INTR] |= 1;
122 s->regs[addr] = value;
128 static CPUReadMemoryFunc *ser_read[] = {
133 static CPUWriteMemoryFunc *ser_write[] = {
138 static void serial_receive(void *opaque, const uint8_t *buf, int size)
140 struct etrax_serial *s = opaque;
142 s->regs[R_INTR] |= 8;
143 s->regs[RS_STAT_DIN] &= ~0xff;
144 s->regs[RS_STAT_DIN] |= (buf[0] & 0xff);
145 s->regs[RS_STAT_DIN] |= (1 << STAT_DAV); /* dav. */
149 static int serial_can_receive(void *opaque)
151 struct etrax_serial *s = opaque;
154 /* Is the receiver enabled? */
155 r = s->regs[RW_REC_CTRL] & 1;
157 /* Pending rx data? */
158 r |= !(s->regs[R_INTR] & 8);
162 static void serial_event(void *opaque, int event)
167 void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
168 target_phys_addr_t base)
170 struct etrax_serial *s;
173 s = qemu_mallocz(sizeof *s);
179 /* transmitter begins ready and idle. */
180 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
181 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
183 qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
186 ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
187 cpu_register_physical_memory (base, R_MAX * 4, ser_regs);