ETRAX: Simplify serport control logic.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c
index d16a14e..80091d5 100644 (file)
--- a/hw/etraxfs_ser.c
+++ b/hw/etraxfs_ser.c
@@ -30,16 +30,17 @@
 
 #define D(x)
 
-#define RW_TR_CTRL     0x00
-#define RW_TR_DMA_EN   0x04
-#define RW_REC_CTRL    0x08
-#define RW_DOUT        0x1c
-#define RS_STAT_DIN    0x20
-#define R_STAT_DIN     0x24
-#define RW_INTR_MASK   0x2c
-#define RW_ACK_INTR    0x30
-#define R_INTR         0x34
-#define R_MASKED_INTR  0x38
+#define RW_TR_CTRL     (0x00 / 4)
+#define RW_TR_DMA_EN   (0x04 / 4)
+#define RW_REC_CTRL    (0x08 / 4)
+#define RW_DOUT        (0x1c / 4)
+#define RS_STAT_DIN    (0x20 / 4)
+#define R_STAT_DIN     (0x24 / 4)
+#define RW_INTR_MASK   (0x2c / 4)
+#define RW_ACK_INTR    (0x30 / 4)
+#define R_INTR         (0x34 / 4)
+#define R_MASKED_INTR  (0x38 / 4)
+#define R_MAX          (0x3c / 4)
 
 #define STAT_DAV     16
 #define STAT_TR_IDLE 22
@@ -51,30 +52,20 @@ struct etrax_serial
        CharDriverState *chr;
        qemu_irq *irq;
 
+       /* This pending thing is a hack.  */
        int pending_tx;
 
        /* Control registers.  */
-       uint32_t rw_tr_ctrl;
-       uint32_t rw_tr_dma_en;
-       uint32_t rw_rec_ctrl;
-       uint32_t rs_stat_din;
-       uint32_t r_stat_din;
-       uint32_t rw_intr_mask;
-       uint32_t rw_ack_intr;
-       uint32_t r_intr;
-       uint32_t r_masked_intr;
+       uint32_t regs[R_MAX];
 };
 
 static void ser_update_irq(struct etrax_serial *s)
 {
-       s->r_intr &= ~(s->rw_ack_intr);
-       s->r_masked_intr = s->r_intr & s->rw_intr_mask;
-
-       D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n", 
-                s->rw_intr_mask, s->r_intr, 
-                s->r_masked_intr, s->rw_ack_intr));
-       qemu_set_irq(s->irq[0], !!s->r_masked_intr);
-       s->rw_ack_intr = 0;
+       s->regs[R_INTR] &= ~(s->regs[RW_ACK_INTR]);
+       s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
+
+       qemu_set_irq(s->irq[0], !!s->regs[R_MASKED_INTR]);
+       s->regs[RW_ACK_INTR] = 0;
 }
 
 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
@@ -83,40 +74,20 @@ static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
        D(CPUState *env = s->env);
        uint32_t r = 0;
 
+       addr >>= 2;
        switch (addr)
        {
-               case RW_TR_CTRL:
-                       r = s->rw_tr_ctrl;
-                       break;
-               case RW_TR_DMA_EN:
-                       r = s->rw_tr_dma_en;
-                       break;
-               case RS_STAT_DIN:
-                       r = s->rs_stat_din;
-                       /* clear dav.  */
-                       s->rs_stat_din &= ~(1 << STAT_DAV);
-                       break;
                case R_STAT_DIN:
-                       r = s->rs_stat_din;
-                       break;
-               case RW_ACK_INTR:
-                       D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
-                       r = s->rw_ack_intr;
+                       r = s->regs[RS_STAT_DIN];
                        break;
-               case RW_INTR_MASK:
-                       r = s->rw_intr_mask;
-                       break;
-               case R_INTR:
-                       D(printf("load r_intr=%x\n", s->r_intr));
-                       r = s->r_intr;
-                       break;
-               case R_MASKED_INTR:
-                       D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
-                       r = s->r_masked_intr;
+               case RS_STAT_DIN:
+                       r = s->regs[addr];
+                       /* Read side-effect: clear dav.  */
+                       s->regs[addr] &= ~(1 << STAT_DAV);
                        break;
-
                default:
-                       D(printf ("%s %x\n", __func__, addr));
+                       r = s->regs[addr];
+                       D(printf ("%s %x=%x\n", __func__, addr, r));
                        break;
        }
        return r;
@@ -129,36 +100,26 @@ ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
        unsigned char ch = value;
        D(CPUState *env = s->env);
 
+       D(printf ("%s %x %x\n",  __func__, addr, value));
+       addr >>= 2;
        switch (addr)
        {
-               case RW_TR_CTRL:
-                       D(printf("rw_tr_ctrl=%x\n", value));
-                       s->rw_tr_ctrl = value;
-                       break;
-               case RW_TR_DMA_EN:
-                       D(printf("rw_tr_dma_en=%x\n", value));
-                       s->rw_tr_dma_en = value;
-                       break;
                case RW_DOUT:
                        qemu_chr_write(s->chr, &ch, 1);
-                       s->r_intr |= 1;
+                       s->regs[R_INTR] |= 1;
                        s->pending_tx = 1;
+                       s->regs[addr] = value;
                        break;
                case RW_ACK_INTR:
-                       D(printf("rw_ack_intr=%x\n", value));
-                       s->rw_ack_intr = value;
-                       if (s->pending_tx && (s->rw_ack_intr & 1)) {
-                               s->r_intr |= 1;
+                       s->regs[addr] = value;
+                       if (s->pending_tx && (s->regs[addr] & 1)) {
+                               s->regs[R_INTR] |= 1;
                                s->pending_tx = 0;
-                               s->rw_ack_intr &= ~1;
+                               s->regs[addr] &= ~1;
                        }
                        break;
-               case RW_INTR_MASK:
-                       D(printf("r_intr_mask=%x\n", value));
-                       s->rw_intr_mask = value;
-                       break;
                default:
-                       D(printf ("%s %x %x\n",  __func__, addr, value));
+                       s->regs[addr] = value;
                        break;
        }
        ser_update_irq(s);
@@ -178,10 +139,10 @@ static void serial_receive(void *opaque, const uint8_t *buf, int size)
 {
        struct etrax_serial *s = opaque;
 
-       s->r_intr |= 8;
-       s->rs_stat_din &= ~0xff;
-       s->rs_stat_din |= (buf[0] & 0xff);
-       s->rs_stat_din |= (1 << STAT_DAV); /* dav.  */
+       s->regs[R_INTR] |= 8;
+       s->regs[RS_STAT_DIN] &= ~0xff;
+       s->regs[RS_STAT_DIN] |= (buf[0] & 0xff);
+       s->regs[RS_STAT_DIN] |= (1 << STAT_DAV); /* dav.  */
        ser_update_irq(s);
 }
 
@@ -191,10 +152,10 @@ static int serial_can_receive(void *opaque)
        int r;
 
        /* Is the receiver enabled?  */
-       r = s->rw_rec_ctrl & 1;
+       r = s->regs[RW_REC_CTRL] & 1;
 
        /* Pending rx data?  */
-       r |= !(s->r_intr & 8);
+       r |= !(s->regs[R_INTR] & 8);
        return r;
 }
 
@@ -216,12 +177,12 @@ void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
        s->chr = chr;
 
        /* transmitter begins ready and idle.  */
-       s->rs_stat_din |= (1 << STAT_TR_RDY);
-       s->rs_stat_din |= (1 << STAT_TR_IDLE);
+       s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
+       s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
 
        qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
                              serial_event, s);
 
        ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
-       cpu_register_physical_memory (base, 0x3c, ser_regs);
+       cpu_register_physical_memory (base, R_MAX * 4, ser_regs);
 }